--- FORCAGE --- -*

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FORCAGE , the speed-independent circuit analysis and synthesis package developed by M. Kishinevsky, A. Kondratyev, A. Taubin, V. Varshavsky et al. at St. Petersburg, Russia, The University of Aizu, Japan and Technical University of Denmark.
It runs on IBM PC's and clones and includes:


analyzes a circuit for speed-independence (semi-modularity) by all states traversal.


analyzes a circuit for speed-independence (distributivity - the most common case of semi-modularity) and constructs a Change Diagram describing behavior of the circuit. Contrary to TRANAL this system implements a polynomial algorithm of a circuit analysis that does not restore all states of the circuit.


verifies implementability of a Change Diagram specification and synthesizes a speed-independent circuit implementing the specification.

A theory underlying the FORCAGE is given in the book:

Michael Kishinevsky, Alex Kondratyev, Alexander Taubin and Victor Varshavsky. "Concurrent Hardware. The Theory and Practice of Self-Timed Design" , John Wiley and Sons, Dec. 1993, ISBN 0471 93536 0.

Sections 1.2 and 2.1 -- a theory for the TRANAL system,

Chapters 1 (Section 1.3), 2, 3 and 6 (sections 6.1 - 6.3) -- a theory for the TRASYN system and

Chapter 4 -- a theory for the TRASPEC system. (for the TRASPEC theory see also the paper of the same authors: "Analysis and Identification of Speed-independent Circuits on an Event Model", Formal Methods in System Design, vol.4, No.1, 1994.)

FORCAGE (for MS-DOS machines) is available through anonymous FTP in .zip format or in .arj format (, /pub/forcage/forcage3.arj) and also from here.
Contact: Michael Kishinevsky:

A program for PERFORMANCE ANALYSIS of speed-independent circuits compatible with FORCAGE is available from here ( Given a (cyclic) Signal Graph as input, it computes the cycle time and critical cycles. It runs under Unix. (Implemented by Christian Nielsen, Technical University of Denmark)


From: Luciano Lavagno ( The specification [in Forcage] is pretty much the same as STG's, except that it does not handle data-dependent computation. I.e. in every "state" of the system only a well defined set of transitions can occur, and in order to model, e.g., read and write cycles of a bus you need to use some "tricks". This apparently is not a great limitation, because the authors have been able to use it to design realistic circuits. The delay model is unbounded gate delays with realistic gates (various types: either NAND/NOR or complex CMOS AND-OR-INVERT gates can be used).

It does:

  • checks of liveness and so on of the specification.
  • synthesis in a technology chosen among one of the available ones (I am aware on NAND/NOR and AND-OR-INVERT).
  • verification of the speed-independence of the implementation (or of hand-designed circuits).

Last Updated: Tue 14 Jun 2005 09:18:28 GMT
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