--- MEAT --- -*

Back To Asynchronous Logic


From: Ken Stevens (
(Taken from the documentation (meat.doc) :)

MEAT -- The Most Excellent Asynchronous Tool, dudes!

This is part of a tool set that was developed here at HP Labs to help with the development of a large 300,000 transistor asynchronous communication chip called the Post Office. During the design of the Post Office, we noticed that an inordinately large amount of time was spent in the process of turning state machine specifications into implementations. Most of this was done in a very "Unger-esque" style, and we figured could be quite easily implemented in Software. Grinding all the minimizations through by had was also very error prone.
Al took the challenge and made Ken a bet that within 3 weeks given a sum of products input he could output correct asynchronous covering using a Quine-McCluskey like algorithm. Well, he got it working, but tuning the performance to make it efficient took several months!
Bill hacked up some code that takes a state machine specification and generates the maximal compatibles. The user then selects the compatibles and his code will do the state assignment and output the unreduced logic equations. This is an Unger like reduction and uses the Tracey algorithm, and is a front end to the asynchronous logic minimizer.
Ken hacked up a back-end to the Logic Minimization that does CMOS transistor minimization, and generates a schematic for the circuit. This was interfaced to the design tool we've been using called Electric(tm), and so it hasn't been included. If you are interested, we can send you the code that does the transistor minimization.
Steve Nowick also interfaced Bill's interface to the Asynchronous Verification tool that is being designed at Stanford under the direction of David Dill. (This is not included, either).
MEAT available on Ken's WWW site

Last Updated: Tue 14 Jun 2005 09:18:28 GMT
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