SYN 2.01, Synthesis of speed-independent circuits
From: Peter Beerel (email@example.com)
SPECIFICATION: State Graph specification description which satisfies
complete state coding (CSC) and is distributive with input choice.
DELAY MODEL: Unbounded gate delay model
- Net list description of speed-independent circuit.
- Specification and implementation files compatible with AVER,
a speed-independent circuit verifier written by Dave Dill
BASIC GATES USED: ANDs, ORs, C_Elements with unlimited fanin and
possible attached input inverters.
CONNECTION WITH OTHER TOOLS:
I have modified a version of SIS to generate the low-level state
graph from an STG. I have also written a converter from extended
burst-mode FSMs (firstname.lastname@example.org, email@example.com)
to state graphs with semi-automated state variable insertion. Both
are available upon request.
EXTENSIONS: SYN 3.0 soon to be available (hopefully): Synthesis
with basic gates with limited fanin.
AVAILABILITY: SYN 2.01 can be obtained through anonymous FTP from
(snooze.stanford.edu). Associated papers (TAU '92 and ICCAD '92) are
CONTACT: Peter A. Beerel, (firstname.lastname@example.org),
AEL 007,Stanford University, Stanford, CA 94305, (415)-723-9510