Tools
--- Versify --- -*

Back To Asynchronous Logic

Versify

Verification of Speed-Independent Circuits
Contributor: Oriol Roig

    versify - VERiFY a Speed-Independent circuit
    versify_stg - VERiFY a Signal Transition Graph
    versify_pn - VERiFY a Petri Net
versify is a CAD tool for the verification of speed-independent circuits against a Signal Transition Graph (STG) specification. The STG describes both the behavior of the environment and the expected behavior of the circuit. Circuit and environment are composed forming a closed system, and the reachability analysis of such a system is performed. A circuit will be correct if it does not generate any unexpected behavior as a reaction to the changes dictated by the environment.

Full details and files for version 2.0

(Previous version).



Last Updated: Tue 14 Jun 2005 09:18:28 GMT
Comments to: jdg@cs.man.ac.uk