(balsa-mgr-technology "common" (description "Base technology.\nNot usable for implementations") (balsa-netlist-options "# doesnt work") (style-options (style-option "sim" (enumeration ("icarus" "Icarus Verilog") ("cver" "Cver") ) "Simulator to use for implementation simulation" ) (style-option "FV" (enumeration ("ovlp" "overlap return-to-zero phases") ("conv" "conventional implementation") ) "FalseVariable implementation style" ) (style-option "PAR" (enumeration ("ovlp" "overlap return-to-zero phases") ("conv" "conventional implementation") ) "Concur implementation style" ) (style-option "SEQ" (enumeration ("ovlp" "overlap return-to-zero phases") ("conv" "conventional implementation") ) "SequenceOptimised implementation style" ) (style-option "suggest-buffers" (boolean) "Add default buffers in suggested drive-up buffer insertion points" ) ) (styles (style "four_b_rb" (style-options (style-option "PP" (enumeration ("broad" "broad output data protocol") ("conv" "conventional implementation") ) "PassivatorPush implementation style" ) ) (description "Bundled data, single-rail, 4-phase broad/reduced-broad") (allowed-style-options "sim" "suggest-buffers" "FV" "PAR" "PP" "SEQ") ) (style "dual_b" (style-options (style-option "logic" (enumeration ("balanced" "`Balanced' logic") ("dims" "DIMS logic implementations") ("ncl" "NCL gates") ) "Style of dual-rail logic" ) (style-option "variable" (enumeration ("sr" "Set-rest flip-flops") ("spacer" "Reset-before-set variables") ("ncl" "NCL pipeline latch") ) "Style of dual-rail variables" ) (style-option "n-of-m-mapping" (boolean) "Unoptimised DIMS enc/decoders") ) (description "Dual-rail with broad sync channels") (allowed-style-options "sim" "suggest-buffers" "logic" "variable" "n-of-m-mapping" "FV" "PAR" "SEQ") ) (style "one_of_2_4" (style-options (style-option "logic" (enumeration ("dims" "DIMS logic implementations") ("ncl" "NCL gates") ) "Style of 1-of-4 logic" ) (style-option "variable" (enumeration ("sr" "Set-rest flip-flops") ("ncl" "NCL pipeline latch") ) "Style of 1-of-4 variables" ) ) (description "1-of-4 with dual rail `odd' bits") (allowed-style-options "sim" "suggest-buffers" "logic" "variable" "FV" "PAR" "SEQ") ) ) )