balsa-tech-xilinx/0000755003172000014400000000000010212064543014342 5ustar tomswapt00000000000000balsa-tech-xilinx/balsa-tech-xilinx0000644003172000014400000000004610212064530017575 0ustar tomswapt00000000000000Xilinx cell library support for Balsa
balsa-tech-xilinx/install-sh0000755003172000014400000001273610212061616016355 0ustar tomswapt00000000000000#!/bin/sh
#
# install - install a program, script, or datafile
# This comes from X11R5 (mit/util/scripts/install.sh).
#
# Copyright 1991 by the Massachusetts Institute of Technology
#
# Permission to use, copy, modify, distribute, and sell this software and its
# documentation for any purpose is hereby granted without fee, provided that
# the above copyright notice appear in all copies and that both that
# copyright notice and this permission notice appear in supporting
# documentation, and that the name of M.I.T. not be used in advertising or
# publicity pertaining to distribution of the software without specific,
# written prior permission. M.I.T. makes no representations about the
# suitability of this software for any purpose. It is provided "as is"
# without express or implied warranty.
#
# Calling this script install-sh is preferred over install.sh, to prevent
# `make' implicit rules from creating a file called install from it
# when there is no Makefile.
#
# This script is compatible with the BSD install script, but was written
# from scratch. It can only install one file at a time, a restriction
# shared with many OS's install programs.
# set DOITPROG to echo to test this script
# Don't use :- since 4.3BSD and earlier shells don't like it.
doit="${DOITPROG-}"
# put in absolute paths if you don't have them in your path; or use env. vars.
mvprog="${MVPROG-mv}"
cpprog="${CPPROG-cp}"
chmodprog="${CHMODPROG-chmod}"
chownprog="${CHOWNPROG-chown}"
chgrpprog="${CHGRPPROG-chgrp}"
stripprog="${STRIPPROG-strip}"
rmprog="${RMPROG-rm}"
mkdirprog="${MKDIRPROG-mkdir}"
transformbasename=""
transform_arg=""
instcmd="$mvprog"
chmodcmd="$chmodprog 0755"
chowncmd=""
chgrpcmd=""
stripcmd=""
rmcmd="$rmprog -f"
mvcmd="$mvprog"
src=""
dst=""
dir_arg=""
while [ x"$1" != x ]; do
case $1 in
-c) instcmd="$cpprog"
shift
continue;;
-d) dir_arg=true
shift
continue;;
-m) chmodcmd="$chmodprog $2"
shift
shift
continue;;
-o) chowncmd="$chownprog $2"
shift
shift
continue;;
-g) chgrpcmd="$chgrpprog $2"
shift
shift
continue;;
-s) stripcmd="$stripprog"
shift
continue;;
-t=*) transformarg=`echo $1 | sed 's/-t=//'`
shift
continue;;
-b=*) transformbasename=`echo $1 | sed 's/-b=//'`
shift
continue;;
*) if [ x"$src" = x ]
then
src=$1
else
# this colon is to work around a 386BSD /bin/sh bug
:
dst=$1
fi
shift
continue;;
esac
done
if [ x"$src" = x ]
then
echo "install: no input file specified"
exit 1
else
true
fi
if [ x"$dir_arg" != x ]; then
dst=$src
src=""
if [ -d $dst ]; then
instcmd=:
chmodcmd=""
else
instcmd=mkdir
fi
else
# Waiting for this to be detected by the "$instcmd $src $dsttmp" command
# might cause directories to be created, which would be especially bad
# if $src (and thus $dsttmp) contains '*'.
if [ -f $src -o -d $src ]
then
true
else
echo "install: $src does not exist"
exit 1
fi
if [ x"$dst" = x ]
then
echo "install: no destination specified"
exit 1
else
true
fi
# If destination is a directory, append the input filename; if your system
# does not like double slashes in filenames, you may need to add some logic
if [ -d $dst ]
then
dst="$dst"/`basename $src`
else
true
fi
fi
## this sed command emulates the dirname command
dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'`
# Make sure that the destination directory exists.
# this part is taken from Noah Friedman's mkinstalldirs script
# Skip lots of stat calls in the usual case.
if [ ! -d "$dstdir" ]; then
defaultIFS='
'
IFS="${IFS-${defaultIFS}}"
oIFS="${IFS}"
# Some sh's can't handle IFS=/ for some reason.
IFS='%'
set - `echo ${dstdir} | sed -e 's@/@%@g' -e 's@^%@/@'`
IFS="${oIFS}"
pathcomp=''
while [ $# -ne 0 ] ; do
pathcomp="${pathcomp}${1}"
shift
if [ ! -d "${pathcomp}" ] ;
then
$mkdirprog "${pathcomp}"
else
true
fi
pathcomp="${pathcomp}/"
done
fi
if [ x"$dir_arg" != x ]
then
$doit $instcmd $dst &&
if [ x"$chowncmd" != x ]; then $doit $chowncmd $dst; else true ; fi &&
if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dst; else true ; fi &&
if [ x"$stripcmd" != x ]; then $doit $stripcmd $dst; else true ; fi &&
if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dst; else true ; fi
else
# If we're going to rename the final executable, determine the name now.
if [ x"$transformarg" = x ]
then
dstfile=`basename $dst`
else
dstfile=`basename $dst $transformbasename |
sed $transformarg`$transformbasename
fi
# don't allow the sed command to completely eliminate the filename
if [ x"$dstfile" = x ]
then
dstfile=`basename $dst`
else
true
fi
# Make a temp file name in the proper directory.
dsttmp=$dstdir/#inst.$$#
# Move or copy the file name to the temp name
$doit $instcmd $src $dsttmp &&
trap "rm -f ${dsttmp}" 0 &&
# and set any options; do chmod last to preserve setuid bits
# If any of these fail, we abort the whole thing. If we want to
# ignore errors from any of these, just make sure not to ignore
# errors from the above "$doit $instcmd $src $dsttmp" command.
if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else true;fi &&
if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi &&
if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else true;fi &&
if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else true;fi &&
# Now rename the file to the real destination.
$doit $rmcmd -f $dstdir/$dstfile &&
$doit $mvcmd $dsttmp $dstdir/$dstfile
fi &&
exit 0
balsa-tech-xilinx/missing0000755003172000014400000002403610212061616015744 0ustar tomswapt00000000000000#! /bin/sh
# Common stub for a few missing GNU programs while installing.
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
# 02111-1307, USA.
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
if test $# -eq 0; then
echo 1>&2 "Try \`$0 --help' for more information"
exit 1
fi
run=:
# In the cases where this matters, `missing' is being run in the
# srcdir already.
if test -f configure.ac; then
configure_ac=configure.ac
else
configure_ac=configure.in
fi
case "$1" in
--run)
# Try to run requested program, and just exit if it succeeds.
run=
shift
"$@" && exit 0
;;
esac
# If it does not exist, or fails to run (possibly an outdated version),
# try to emulate it.
case "$1" in
-h|--h|--he|--hel|--help)
echo "\
$0 [OPTION]... PROGRAM [ARGUMENT]...
Handle \`PROGRAM [ARGUMENT]...' for when PROGRAM is missing, or return an
error status if there is no known handling for PROGRAM.
Options:
-h, --help display this help and exit
-v, --version output version information and exit
--run try to run the given command, and emulate it if it fails
Supported PROGRAM values:
aclocal touch file \`aclocal.m4'
autoconf touch file \`configure'
autoheader touch file \`config.h.in'
automake touch all \`Makefile.in' files
bison create \`y.tab.[ch]', if possible, from existing .[ch]
flex create \`lex.yy.c', if possible, from existing .c
help2man touch the output file
lex create \`lex.yy.c', if possible, from existing .c
makeinfo touch the output file
tar try tar, gnutar, gtar, then tar without non-portable flags
yacc create \`y.tab.[ch]', if possible, from existing .[ch]"
;;
-v|--v|--ve|--ver|--vers|--versi|--versio|--version)
echo "missing 0.4 - GNU automake"
;;
-*)
echo 1>&2 "$0: Unknown \`$1' option"
echo 1>&2 "Try \`$0 --help' for more information"
exit 1
;;
aclocal*)
if test -z "$run" && ($1 --version) > /dev/null 2>&1; then
# We have it, but it failed.
exit 1
fi
echo 1>&2 "\
WARNING: \`$1' is missing on your system. You should only need it if
you modified \`acinclude.m4' or \`${configure_ac}'. You might want
to install the \`Automake' and \`Perl' packages. Grab them from
any GNU archive site."
touch aclocal.m4
;;
autoconf)
if test -z "$run" && ($1 --version) > /dev/null 2>&1; then
# We have it, but it failed.
exit 1
fi
echo 1>&2 "\
WARNING: \`$1' is missing on your system. You should only need it if
you modified \`${configure_ac}'. You might want to install the
\`Autoconf' and \`GNU m4' packages. Grab them from any GNU
archive site."
touch configure
;;
autoheader)
if test -z "$run" && ($1 --version) > /dev/null 2>&1; then
# We have it, but it failed.
exit 1
fi
echo 1>&2 "\
WARNING: \`$1' is missing on your system. You should only need it if
you modified \`acconfig.h' or \`${configure_ac}'. You might want
to install the \`Autoconf' and \`GNU m4' packages. Grab them
from any GNU archive site."
files=`sed -n 's/^[ ]*A[CM]_CONFIG_HEADER(\([^)]*\)).*/\1/p' ${configure_ac}`
test -z "$files" && files="config.h"
touch_files=
for f in $files; do
case "$f" in
*:*) touch_files="$touch_files "`echo "$f" |
sed -e 's/^[^:]*://' -e 's/:.*//'`;;
*) touch_files="$touch_files $f.in";;
esac
done
touch $touch_files
;;
automake*)
if test -z "$run" && ($1 --version) > /dev/null 2>&1; then
# We have it, but it failed.
exit 1
fi
echo 1>&2 "\
WARNING: \`$1' is missing on your system. You should only need it if
you modified \`Makefile.am', \`acinclude.m4' or \`${configure_ac}'.
You might want to install the \`Automake' and \`Perl' packages.
Grab them from any GNU archive site."
find . -type f -name Makefile.am -print |
sed 's/\.am$/.in/' |
while read f; do touch "$f"; done
;;
autom4te)
if test -z "$run" && ($1 --version) > /dev/null 2>&1; then
# We have it, but it failed.
exit 1
fi
echo 1>&2 "\
WARNING: \`$1' is needed, and you do not seem to have it handy on your
system. You might have modified some files without having the
proper tools for further handling them.
You can get \`$1Help2man' as part of \`Autoconf' from any GNU
archive site."
file=`echo "$*" | sed -n 's/.*--output[ =]*\([^ ]*\).*/\1/p'`
test -z "$file" && file=`echo "$*" | sed -n 's/.*-o[ ]*\([^ ]*\).*/\1/p'`
if test -f "$file"; then
touch $file
else
test -z "$file" || exec >$file
echo "#! /bin/sh"
echo "# Created by GNU Automake missing as a replacement of"
echo "# $ $@"
echo "exit 0"
chmod +x $file
exit 1
fi
;;
bison|yacc)
echo 1>&2 "\
WARNING: \`$1' is missing on your system. You should only need it if
you modified a \`.y' file. You may need the \`Bison' package
in order for those modifications to take effect. You can get
\`Bison' from any GNU archive site."
rm -f y.tab.c y.tab.h
if [ $# -ne 1 ]; then
eval LASTARG="\${$#}"
case "$LASTARG" in
*.y)
SRCFILE=`echo "$LASTARG" | sed 's/y$/c/'`
if [ -f "$SRCFILE" ]; then
cp "$SRCFILE" y.tab.c
fi
SRCFILE=`echo "$LASTARG" | sed 's/y$/h/'`
if [ -f "$SRCFILE" ]; then
cp "$SRCFILE" y.tab.h
fi
;;
esac
fi
if [ ! -f y.tab.h ]; then
echo >y.tab.h
fi
if [ ! -f y.tab.c ]; then
echo 'main() { return 0; }' >y.tab.c
fi
;;
lex|flex)
echo 1>&2 "\
WARNING: \`$1' is missing on your system. You should only need it if
you modified a \`.l' file. You may need the \`Flex' package
in order for those modifications to take effect. You can get
\`Flex' from any GNU archive site."
rm -f lex.yy.c
if [ $# -ne 1 ]; then
eval LASTARG="\${$#}"
case "$LASTARG" in
*.l)
SRCFILE=`echo "$LASTARG" | sed 's/l$/c/'`
if [ -f "$SRCFILE" ]; then
cp "$SRCFILE" lex.yy.c
fi
;;
esac
fi
if [ ! -f lex.yy.c ]; then
echo 'main() { return 0; }' >lex.yy.c
fi
;;
help2man)
if test -z "$run" && ($1 --version) > /dev/null 2>&1; then
# We have it, but it failed.
exit 1
fi
echo 1>&2 "\
WARNING: \`$1' is missing on your system. You should only need it if
you modified a dependency of a manual page. You may need the
\`Help2man' package in order for those modifications to take
effect. You can get \`Help2man' from any GNU archive site."
file=`echo "$*" | sed -n 's/.*-o \([^ ]*\).*/\1/p'`
if test -z "$file"; then
file=`echo "$*" | sed -n 's/.*--output=\([^ ]*\).*/\1/p'`
fi
if [ -f "$file" ]; then
touch $file
else
test -z "$file" || exec >$file
echo ".ab help2man is required to generate this page"
exit 1
fi
;;
makeinfo)
if test -z "$run" && (makeinfo --version) > /dev/null 2>&1; then
# We have makeinfo, but it failed.
exit 1
fi
echo 1>&2 "\
WARNING: \`$1' is missing on your system. You should only need it if
you modified a \`.texi' or \`.texinfo' file, or any other file
indirectly affecting the aspect of the manual. The spurious
call might also be the consequence of using a buggy \`make' (AIX,
DU, IRIX). You might want to install the \`Texinfo' package or
the \`GNU make' package. Grab either from any GNU archive site."
file=`echo "$*" | sed -n 's/.*-o \([^ ]*\).*/\1/p'`
if test -z "$file"; then
file=`echo "$*" | sed 's/.* \([^ ]*\) *$/\1/'`
file=`sed -n '/^@setfilename/ { s/.* \([^ ]*\) *$/\1/; p; q; }' $file`
fi
touch $file
;;
tar)
shift
if test -n "$run"; then
echo 1>&2 "ERROR: \`tar' requires --run"
exit 1
fi
# We have already tried tar in the generic part.
# Look for gnutar/gtar before invocation to avoid ugly error
# messages.
if (gnutar --version > /dev/null 2>&1); then
gnutar "$@" && exit 0
fi
if (gtar --version > /dev/null 2>&1); then
gtar "$@" && exit 0
fi
firstarg="$1"
if shift; then
case "$firstarg" in
*o*)
firstarg=`echo "$firstarg" | sed s/o//`
tar "$firstarg" "$@" && exit 0
;;
esac
case "$firstarg" in
*h*)
firstarg=`echo "$firstarg" | sed s/h//`
tar "$firstarg" "$@" && exit 0
;;
esac
fi
echo 1>&2 "\
WARNING: I can't seem to be able to run \`tar' with the given arguments.
You may want to install GNU tar or Free paxutils, or check the
command line arguments."
exit 1
;;
*)
echo 1>&2 "\
WARNING: \`$1' is needed, and you do not seem to have it handy on your
system. You might have modified some files without having the
proper tools for further handling them. Check the \`README' file,
it often tells you about the needed prerequirements for installing
this package. You may also peek at any GNU archive site, in case
some other package would contain this missing \`$1' program."
exit 1
;;
esac
exit 0
balsa-tech-xilinx/AUTHORS0000644003172000014400000000021710212062642015410 0ustar tomswapt00000000000000
Balsa Team (balsa@cs.man.ac.uk)
APT Group, Dept. of Computer Science,
The University of Manchester,
Manchester
M13 9PL, UK
balsa-tech-xilinx/README0000644003172000014400000000047010212064345015223 0ustar tomswapt00000000000000 |_ _ | _ _ |_ _ _ |_ _ _.|.._ _ _ [ Balsa system Xilinx technology ]
|_)(_\|_/ (_\ - |_(-'(_.| | - _/_|||| |_/_ For Balsa version 3
(C) 2005 AMULET Group, Dept. of Computer Science,
The University of Manchester,
Manchester
M13 9PL, UK
balsa-tech-xilinx/NEWS0000644003172000014400000000003210212061616015032 0ustar tomswapt00000000000000This is the first version
balsa-tech-xilinx/configure.in0000644003172000014400000000043010212064671016652 0ustar tomswapt00000000000000dnl Process this file with autoconf to produce a configure script
AC_INIT(xilinx/xilinx)
AM_INIT_AUTOMAKE(balsa-tech-xil, 0.0.1)
AC_PROG_INSTALL
AC_PREFIX_DEFAULT(`balsa-config -d`)
balsadatadir=${prefix}/share
AC_SUBST(balsadatadir)
AC_OUTPUT([
Makefile
xilinx/Makefile
])
balsa-tech-xilinx/Makefile.am0000644003172000014400000000014410212064703016373 0ustar tomswapt00000000000000## Process this file with automake to produce Makefile.in
SUBDIRS = xilinx
EXTRA_DIST = bootstrap
balsa-tech-xilinx/xilinx/0000755003172000014400000000000010212061546015655 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/gate-mappings-caps0000644003172000014400000002757410212061546021277 0ustar tomswapt00000000000000;;;
;;; `gate-mappings-caps'
;;; Abstract->concrete gate mappings, for Xilinx 'Generic' technology
;;;
;;; 02 Jun 2004, Sam Taylor
;;; 02 Jul 1999, Andrew Bardsley
;;;
;;; This file has lists of (abs-gate-name default-real-gate . weighted-real-gates)
;;; The default real gate is used where nodal load management is not used and has the form:
;;; (gate-name . pin-mappings)
;;; The weighted-real-gates have the form:
;;; (output-drive gate-name . pin-mappings)
;;; The pin-mappings are lists of integers mapping abstract gate pin numbers to real gate pin
;;; numbers. The integers correspond to abstract gate pin positions (0 based) and their position
;;; to the position of that pin in the real gate. eg.
;;; (0 "q1and2d0" 2 1 0) is a drive 0 2-input and gate where pin 2 of the abstract gate (in2) is
;;; pin 0 of the real gate.
;;; and{n}: out,in1,in2...
("and2" ("AND2" 0 1 2) (1 "AND2"))
("and3" ("AND3" 0 1 2 3) (1 "AND3"))
("and4" ("AND4" 0 1 2 3 4) (1 "AND4"))
("and5" ("AND5" 0 1 2 3 4 5) (1 "AND5"))
;;; nand{n}: out,in1,in2...
("nand2" ("NAND2" 0 1 2) (1 "NAND2"))
("nand3" ("NAND3" 0 1 2 3) (1 "NAND3"))
("nand4" ("NAND4" 0 1 2 3 4) (1 "NAND4"))
("nand5" ("NAND5" 0 1 2 3 4 5) (1 "NAND5"))
;;; or{n}: out,in1,in2...
("or2" ("OR2" 0 1 2) (1 "OR2"))
("or3" ("OR3" 0 1 2 3) (1 "OR3"))
("or4" ("OR4" 0 1 2 3 4) (1 "OR4"))
("or5" ("OR5" 0 1 2 3 4 5) (1 "OR5"))
;;; nor{n}: out,in1,in2...
("nor2" ("NOR2" 0 1 2) (1 "NOR2"))
("nor3" ("NOR3" 0 1 2 3) (1 "NOR3"))
("nor4" ("NOR4" 0 1 2 3 4) (1 "NOR4"))
("nor5" ("NOR5" 0 1 2 3 4 5) (1 "NOR5"))
;;; xor2: out,in1,in2
("xor2" ("XOR2" 0 1 2) (1 "XOR2"))
;;; xnor2: out,in1,in2
("xnor2" ("XNOR2" 0 1 2) (1 "XNOR2"))
;;; inv: out,in
("inv" ("INV" 0 1) (1 "INV"))
;;; NB. buf is a driving buffer not a logical buffer
;;; buf: out,in
("buf" ("BUF" 0 1) (1 "BUF") (2 "BU2") (3 "BU3") (4 "BU4") (8 "BU8"))
("suggested-buffer" ("BUF" 0 1) (1 "BUF"))
;;; NB. connect is a logical buffer
;;; connect: out,in
("connect" ("BUF" 0 1) (1 "BUF"))
;;; latch: in,out,enable
("latch" ("FD" 2 0 1) (1 "FD"))
;;; Edge Triggered Flip Flop with async clear
("edge-dff-clr" ("FDC" 3 1 2 0) (1 "FDC"))
("adder" ("balsa_fa" 0 1 2 3 4 5 6 7) (1 "balsa_fa"))
;;; mutex: inA,inB,outA,outB
;;; mutual exclusion unit
("mutex" ("mutex1" 2 3 0 1) (1 "mutex1"))
;; helper cells
("and-or22" ("ao22" 0 1 2 3 4) (1 "ao22"))
("and-or-invert22" ("aoi22" 0 1 2 3 4) (1 "aoi22"))
("and-or222" ("ao222" 0 1 2 3 4 5 6) (1 "ao222"))
("and-or-invert222" ("aoi222" 0 1 2 3 4 5 6) (1 "aoi222"))
("set-reset-flip-flop" ("srff" 0 1 2 3) (1 "srff"))
("mux2" ("mux2" 0 1 2 3) (1 "mux2"))
("nmux2" ("nmux2" 0 1 2 3) (1 "nmux2"))
("single-rail-full-adder" ("balsa_fa" 0 1 2 3 4 5 6 7) (1 "balsa_fa"))
("c-element2" ("c2" 0 1 2) (1 "c2"))
("c-element3" ("c3" 0 1 2 3) (1 "c3"))
("inverted-c-element" ("nc2" 0 1 2) (1 "nc2"))
("inverted-assym-c-element" ("nc2p" 0 1 2) (1 "nc2p"))
("demux2" ("demux2" 0 1 2 3) (1 "demux2"))
("s-element" ("selem" 0 1 2 3) (1 "selem"))
("th22" ("th22" 0 1 2) (1 "th22"))
("th33" ("th33" 0 1 2 3) (1 "th33"))
("th23" ("th23" 0 1 2 3) (1 "th23"))
("th23w2" ("th23w2" 0 1 2 3) (1 "th23w2"))
("th24" ("th24" 0 1 2 3 4) (1 "th24"))
("th24w2" ("th24w2" 0 1 2 3 4) (1 "th24w2"))
("th24w22" ("th24w22" 0 1 2 3 4) (1 "th24w22"))
("th33w2" ("th33w2" 0 1 2 3) (1 "th33w2"))
("th34" ("th34" 0 1 2 3 4) (1 "th34"))
("th34w2" ("th34w2" 0 1 2 3 4) (1 "th34w2"))
("th34w22" ("th34w22" 0 1 2 3 4) (1 "th34w22"))
("dual-rail-and2" ("dr_and2" 0 1 2 3 4 5) (1 "dr_and2"))
("dual-rail-and2-bal" ("dr_and2_bal" 0 1 2 3 4 5) (1 "dr_and2_bal"))
("dual-rail-and2-ncl" ("dr_and2_ncl" 0 1 2 3 4 5) (1 "dr_and2_ncl"))
("dual-rail-or2" ("dr_or2" 0 1 2 3 4 5) (1 "dr_or2"))
("dual-rail-or2-bal" ("dr_or2_bal" 0 1 2 3 4 5) (1 "dr_or2_bal"))
("dual-rail-or2-ncl" ("dr_or2_ncl" 0 1 2 3 4 5) (1 "dr_or2_ncl"))
("dual-rail-nor2" ("dr_nor2" 0 1 2 3 4 5) (1 "dr_nor2"))
("dual-rail-nor2-ncl" ("dr_nor2_ncl" 0 1 2 3 4 5) (1 "dr_nor2_ncl"))
("dual-rail-xor2" ("dr_xor2" 0 1 2 3 4 5) (1 "dr_xor2"))
("dual-rail-xor2-ncl" ("dr_xor2_ncl" 0 1 2 3 4 5) (1 "dr_xor2_ncl"))
("dual-rail-ao21" ("dr_ao21" 0 1 2 3 4 5 6 7) (1 "dr_ao21"))
("dual-rail-ao21-bal" ("dr_ao21_bal" 0 1 2 3 4 5 6 7) (1 "dr_ao21_bal"))
("dual-rail-ao21-ncl" ("dr_ao21_ncl" 0 1 2 3 4 5 6 7) (1 "dr_ao21_ncl"))
("dual-rail-ineq-comp" ("dr_ineq_comp" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp"))
("dual-rail-ineq-comp-bal" ("dr_ineq_comp_bal" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp_bal"))
("dual-rail-ineq-comp-ncl" ("dr_ineq_comp_ncl" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp_ncl"))
("dual-rail-mux2" ("dr_mux2" 0 1 2 3 4 5 6 7) (1 "dr_mux2"))
("dual-rail-mux2-ncl" ("dr_mux2_ncl" 0 1 2 3 4 5 6 7) (1 "dr_mux2_ncl"))
("dual-rail-half-adder" ("dr_ha" 0 1 2 3 4 5 6 7) (1 "dr_ha"))
("dual-rail-half-adder-bal" ("dr_ha_bal" 0 1 2 3 4 5 6 7) (1 "dr_ha_bal"))
("dual-rail-half-adder-ncl" ("dr_ha_ncl" 0 1 2 3 4 5 6 7) (1 "dr_ha_ncl"))
("dual-rail-full-adder" ("dr_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_fa"))
("dual-rail-full-adder-bal" ("dr_fa_bal" 0 1 2 3 4 5 6 7 8 9) (1 "dr_fa_bal"))
("dual-rail-dims-adder" ("dr_dims_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_dims_fa"))
("dual-rail-ncl-adder" ("dr_ncl_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_ncl_fa"))
("dual-rail-full-adder-primed" ("dr_fa_p" 0 1 2 3 4 5 6 7) (1 "dr_fa_p"))
("dual-rail-full-adder-primed-bal" ("dr_fa_p_bal" 0 1 2 3 4 5 6 7) (1 "dr_fa_p_bal"))
("dual-rail-full-adder-primed-ncl" ("dr_fa_p_ncl" 0 1 2 3 4 5 6 7) (1 "dr_fa_p_ncl"))
("dual-rail-dims-subtracter" ("dr_dims_fs" 0 1 2 3 4 5 6 7 8 9) (1 "dr_dims_fs"))
("dual-rail-ncl-subtracter" ("dr_ncl_fs" 0 1 2 3 4 5 6 7 8 9) (1 "dr_ncl_fs"))
("one-of-four-half-adder" ("oof_ha" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ha"))
("one-of-four-dims-carry-adder" ("oof_dims_ca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_ca"))
("one-of-four-ncl-carry-adder" ("oof_ncl_ca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_ca"))
("oof_dims_ca_se" ("oof_dims_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dims_ca_se"))
("one-of-four-dims-carry-adder-overflow" ("oof_ncl_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ncl_ca_se"))
("one-of-four-full-adder" ("oof_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_fa"))
("one-of-four-dims-full-adder" ("oof_dims_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dims_fa"))
("one-of-four-dims-full-adder-overflow" ("oof_dims_fa_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17) (1 "oof_dims_fa_se"))
("one-of-four-dims-subtracter" ("oof_dims_fs" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dims_fs"))
("one-of-four-ncl-full-adder" ("oof_ncl_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_ncl_fa"))
("one-of-four-ncl-full-adder-overflow" ("oof_ncl_fa_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17) (1 "oof_ncl_fa_se"))
("one-of-four-ncl-subtracter" ("oof_ncl_fs" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_ncl_fs"))
("one-of-four-dims-primed-carry-adder" ("oof_dims_pca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_pca"))
("one-of-four-ncl-primed-carry-adder" ("oof_ncl_pca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_pca"))
("one-of-four-dims-primed-carry-adder-overflow" ("oof_dims_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dims_pca_se"))
("one-of-four-ncl-primed-carry-adder-overflow" ("oof_ncl_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ncl_pca_se"))
("one-of-four-dual-rail-dims-carry-adder" ("oof_dr_dims_ca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_dims_ca"))
("one-of-four-dual-rail-ncl-carry-adder" ("oof_dr_ncl_ca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_ncl_ca"))
("one-of-four-dual-rail-dims-carry-adder-overflow" ("oof_dr_dims_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_dims_ca_se"))
("one-of-four-dual-rail-ncl-carry-adder-overflow" ("oof_dr_ncl_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_ncl_ca_se"))
("one-of-four-dual-rail-dims-primed-carry-adder" ("oof_dr_dims_pca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_dims_pca"))
("one-of-four-dual-rail-ncl-primed-carry-adder" ("oof_dr_ncl_pca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_ncl_pca"))
("one-of-four-dual-rail-dims-primed-carry-adder-overflow" ("oof_dr_dims_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_dims_pca_se"))
("one-of-four-dual-rail--ncl-primed-carry-adder-overflow" ("oof_dr_ncl_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_ncl_pca_se"))
("one-of-four-dims-and2" ("oof_dims_and2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_and2"))
("one-of-four-ncl-and2" ("oof_ncl_and2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_and2"))
("one-of-four-dims-or2" ("oof_dims_or2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_or2"))
("one-of-four-ncl-or2" ("oof_ncl_or2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_or2"))
("one-of-four-dims-xor2" ("oof_dims_xor2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_xor2"))
("one-of-four-ncl-xor2" ("oof_ncl_xor2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_xor2"))
("oof_dims_equal" ("oof_dims_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_equal"))
("oof_ncl_equal" ("oof_ncl_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_equal"))
("oof_dr_dims_equal" ("oof_dr_dims_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dr_dims_equal"))
("oof_dr_ncl_equal" ("oof_dr_ncl_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dr_ncl_equal"))
("one-of-four-dims-inequal" ("oof_dims_inequal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_inequal"))
("one-of-four-ncl-inequal" ("oof_ncl_inequal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_inequal"))
("oof_dr_dims_inequal" ("oof_dr_dims_inequal" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_inequal"))
("one-of-four-dual-rail-ncl-inequal" ("oof_dr_ncl_inequal" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_inequal"))
("one-of-four-dims-comp" ("oof_dims_comp" 0 1 2 3 4 5 6 7 8 9 10) (1 "oof_dims_comp"))
("one-of-four-ncl-comp" ("oof_ncl_comp" 0 1 2 3 4 5 6 7 8 9 10) (1 "oof_ncl_comp"))
("oof_dr_dims_ineq_comp" ("oof_dr_dims_ineq_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_dims_ineq_comp"))
("oof_dr_ncl_ineq_comp" ("oof_dr_ncl_ineq_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_ncl_ineq_comp"))
("oof_dr_dims_ineq_sgn_comp" ("oof_dr_dims_ineq_sgn_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_dims_ineq_sgn_comp"))
("oof_dr_ncl_ineq_sgn_comp" ("oof_dr_ncl_ineq_sgn_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_ncl_ineq_sgn_comp"))
("one-of-four-dims-less-than" ("oof_dims_lt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_lt"))
("one-of-four-ncl-less-than" ("oof_ncl_lt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_lt"))
("one-of-four-dims-greater-than" ("oof_dims_gt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_gt"))
("one-of-four-ncl-greater-than" ("oof_ncl_gt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_gt"))
("one-of-four-dual-rail-dims-less-than" ("oof_dr_dims_lt" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_lt"))
("one-of-four-dual-rail-ncl-less-than" ("oof_dr_ncl_lt" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_lt"))
("one-of-four-dual-rail-dims-greater-than" ("oof_dr_dims_gt" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_gt"))
("one-of-four-dual-rail-ncl-greater-than" ("oof_dr_ncl_gt" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_gt"))
("dual-rail-dims-comp" ("dr_dims_comp" 0 1 2 3 4 5 6) (1 "dr_dims_comp"))
("dual-rail-ncl-comp" ("dr_ncl_comp" 0 1 2 3 4 5 6) (1 "dr_ncl_comp"))
("dual-rail-dims-less-than" ("dr_dims_lt" 0 1 2 3 4 5) (1 "dr_dims_lt"))
("dual-rail-ncl-less-than" ("dr_ncl_lt" 0 1 2 3 4 5) (1 "dr_ncl_lt"))
("dual-rail-dims-greater-than" ("dr_dims_gt" 0 1 2 3 4 5) (1 "dr_dims_gt"))
("dual-rail-ncl-greater-than" ("dr_ncl_gt" 0 1 2 3 4 5) (1 "dr_ncl_gt"))
("one-of-three-dual-rail-dims-comp" ("dr_oot_dims_comp" 0 1 2 3 4 5 6) (1 "dr_oot_dims_comp"))
("one-of-three-dual-rail-ncl-comp" ("dr_oot_ncl_comp" 0 1 2 3 4 5 6) (1 "dr_oot_ncl_comp"))
("one-of-three-dims-comp" ("oot_dims_comp" 0 1 2 3 4 5 6 7 8) (1 "oot_dims_comp"))
("one-of-three-ncl-comp" ("oot_ncl_comp" 0 1 2 3 4 5 6 7 8) (1 "oot_ncl_comp"))
("dual-rail-latch" ("dr_latch" 0 1 2 3 4) (1 "dr_latch"))
("dual-rail-spacer-latch" ("dr_spacer_latch" 0 1 2 3 4) (1 "dr_spacer_latch"))
("dual-rail-ncl-latch" ("dr_ncl_latch" 0 1 2 3 4) (1 "dr_ncl_latch"))
("dual-rail-true-ncl-latch" ("dr_tncl_latch" 0 1 2 3 4 5) (1 "dr_tncl_latch"))
("one-of-four-latch" ("oof_latch" 0 1 2 3 4 5 6 7 8) (1 "oof_latch"))
("one-of-four-ncl-latch" ("oof_ncl_latch" 0 1 2 3 4 5 6 7 8) (1 "oof_ncl_latch"))
("one-of-four-true-ncl-reg" ("oof_tncl_latch" 0 1 2 3 4 5 6 7 8 9) (1 "oof_tncl_latch"))
balsa-tech-xilinx/xilinx/balsa-cells-caps.net0000644003172000014400000042514510212067676021520 0ustar tomswapt00000000000000;;; `balsa-cells-caps.net'
;;; xilinx Balsa helper cells
;;; Created: Wed Jun 2 13:19:59 BST 2004
;;; By: Sam Taylor (Linux)
;;; With net-net version: 20031009
(circuit "mutex1"
(ports
("q0" output 1)
("q1" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "NAND2" (("int_0n" 0) "i0" ("int_0n" 1)))
(instance "NAND2" (("int_0n" 1) "i1" ("int_0n" 0)))
(instance "NOR3" ("q0" ("int_0n" 0) ("int_0n" 0) ("int_0n" 0)))
(instance "NOR3" ("q1" ("int_0n" 1) ("int_0n" 1) ("int_0n" 1)))
)
(attributes (cell-type "helper"))
)
(circuit "ao22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "OR2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "AND2" (("int_0n" 1) "i2" "i3"))
(instance "AND2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "aoi22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "NOR2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "AND2" (("int_0n" 1) "i2" "i3"))
(instance "AND2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "ao222"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
("i4" input 1)
("i5" input 1)
)
(nets
("int_0n" 3)
)
(instances
(instance "OR3" ("q" ("int_0n" 0) ("int_0n" 1) ("int_0n" 2)))
(instance "AND2" (("int_0n" 2) "i4" "i5"))
(instance "AND2" (("int_0n" 1) "i2" "i3"))
(instance "AND2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "aoi222"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
("i4" input 1)
("i5" input 1)
)
(nets
("int_0n" 3)
)
(instances
(instance "NOR3" ("q" ("int_0n" 0) ("int_0n" 1) ("int_0n" 2)))
(instance "AND2" (("int_0n" 2) "i4" "i5"))
(instance "AND2" (("int_0n" 1) "i2" "i3"))
(instance "AND2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "srff"
(ports
("s" input 1)
("r" input 1)
("q" output 1)
("nq" output 1)
)
(nets
)
(instances
(instance "NOR2" ("nq" "q" "s"))
(instance "NOR2" ("q" "nq" "r"))
)
(attributes (simulation-initialise ("q" 0)) (cell-type "helper"))
)
(circuit "mux2"
(ports
("q" output 1)
("d0" input 1)
("d1" input 1)
("sel" input 1)
)
(nets
("int_0n" 2)
("nsel_0n" 1)
)
(instances
(instance "NAND2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "NAND2" (("int_0n" 1) "d1" "sel"))
(instance "NAND2" (("int_0n" 0) "d0" ("nsel_0n" 0)))
(instance "INV" (("nsel_0n" 0) "sel"))
)
(attributes (cell-type "helper"))
)
(circuit "nmux2"
(ports
("q" output 1)
("d0" input 1)
("d1" input 1)
("sel" input 1)
)
(nets
("int_0n" 2)
("nsel_0n" 1)
("nq_0n" 1)
)
(instances
(instance "INV" ("q" ("nq_0n" 0)))
(instance "NAND2" (("nq_0n" 0) ("int_0n" 0) ("int_0n" 1)))
(instance "NAND2" (("int_0n" 1) "d1" "sel"))
(instance "NAND2" (("int_0n" 0) "d0" ("nsel_0n" 0)))
(instance "INV" (("nsel_0n" 0) "sel"))
)
(attributes (cell-type "helper"))
)
(circuit "balsa_fa"
(ports
("nStart" input 1)
("A" input 1)
("B" input 1)
("nCVi" input 1)
("Ci" input 1)
("nCVo" output 1)
("Co" output 1)
("sum" output 1)
)
(nets
("start_0n" 1)
("ha_0n" 1)
("cv_0n" 1)
)
(instances
(instance "XOR2" ("sum" ("ha_0n" 0) "Ci"))
(instance "XOR2" (("ha_0n" 0) "A" "B"))
(instance "mux2" ("Co" "A" "Ci" ("ha_0n" 0)))
(instance "nmux2" ("nCVo" ("start_0n" 0) ("cv_0n" 0) ("ha_0n" 0)))
(instance "NOR2" (("cv_0n" 0) "nStart" "nCVi"))
(instance "INV" (("start_0n" 0) "nStart"))
)
(attributes (cell-type "helper"))
)
(circuit "c2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
)
(instances
(instance "ao222" ("q" "i0" "i1" "i0" "q" "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "c3"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("qint_0n" 1)
)
(instances
(instance "c2" ("q" "i2" ("qint_0n" 0)))
(instance "c2" (("qint_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "nc2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("nq_0n" 1)
)
(instances
(instance "aoi222" ("q" "i0" "i1" "i0" ("nq_0n" 0) "i1" ("nq_0n" 0)))
(instance "INV" (("nq_0n" 0) "q"))
)
(attributes (cell-type "helper"))
)
(circuit "nc2p"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("nq_0n" 1)
)
(instances
(instance "aoi22" ("q" "i0" "i1" "i0" ("nq_0n" 0)))
(instance "INV" (("nq_0n" 0) "q"))
)
(attributes (cell-type "helper"))
)
(circuit "demux2"
(ports
("i" input 1)
("o0" output 1)
("o1" output 1)
("s" input 1)
)
(nets
("ns_0n" 1)
)
(instances
(instance "AND2" ("o1" "i" "s"))
(instance "AND2" ("o0" "i" ("ns_0n" 0)))
(instance "INV" (("ns_0n" 0) "s"))
)
(attributes (cell-type "helper"))
)
(circuit "selem"
(ports
("Ar" input 1)
("Aa" output 1)
("Br" output 1)
("Ba" input 1)
)
(nets
("s_0n" 1)
)
(instances
(instance "nc2p" (("s_0n" 0) "Ar" "Ba"))
(instance "NOR2" ("Aa" "Ba" ("s_0n" 0)))
(instance "AND2" ("Br" "Ar" ("s_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "th22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("qint_0n" 3)
)
(instances
(instance "OR3" ("q" ("qint_0n" 0) ("qint_0n" 1) ("qint_0n" 2)))
(instance "AND2" (("qint_0n" 2) "i1" "q"))
(instance "AND2" (("qint_0n" 1) "i0" "q"))
(instance "AND2" (("qint_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "th33"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("qint_0n" 2)
)
(instances
(instance "OR2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "OR3" (("qint_0n" 1) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "AND2" (("qint_0n" 0) "i1" "i2"))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th23"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 2)
("qint_0n" 2)
("sinti_0n" 1)
)
(instances
(instance "OR2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "OR2" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1)))
(instance "AND2" (("sint_0n" 1) "i0" ("sinti_0n" 0)))
(instance "AND2" (("sint_0n" 0) "i1" "i2"))
(instance "OR2" (("sinti_0n" 0) "i1" "i2"))
(instance "OR3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th23w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 2)
("sint_0n" 1)
)
(instances
(instance "OR4" ("q" "i0" ("hint_0n" 0) ("hint_0n" 1) ("sint_0n" 0)))
(instance "AND2" (("sint_0n" 0) "i1" "i2"))
(instance "AND2" (("hint_0n" 1) "i2" "q"))
(instance "AND2" (("hint_0n" 0) "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 4)
("sint_0n" 6)
("qint_0n" 3)
)
(instances
(instance "OR3" ("q" ("qint_0n" 0) ("qint_0n" 1) ("qint_0n" 2)))
(instance "OR3" (("qint_0n" 2) ("sint_0n" 3) ("sint_0n" 4) ("sint_0n" 5)))
(instance "OR3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "AND2" (("sint_0n" 5) "i2" "i3"))
(instance "AND2" (("sint_0n" 4) "i1" "i3"))
(instance "AND2" (("sint_0n" 3) "i1" "i2"))
(instance "AND2" (("sint_0n" 2) "i0" "i3"))
(instance "AND2" (("sint_0n" 1) "i0" "i2"))
(instance "AND2" (("sint_0n" 0) "i0" "i1"))
(instance "OR4" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2) ("hint_0n" 3)))
(instance "AND2" (("hint_0n" 3) "i3" "q"))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 3)
("qint_0n" 2)
)
(instances
(instance "OR3" ("q" ("qint_0n" 0) ("qint_0n" 1) "i0"))
(instance "OR3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "AND2" (("sint_0n" 2) "i2" "i3"))
(instance "AND2" (("sint_0n" 1) "i1" "i3"))
(instance "AND2" (("sint_0n" 0) "i1" "i2"))
(instance "OR3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "AND2" (("hint_0n" 2) "i3" "q"))
(instance "AND2" (("hint_0n" 1) "i2" "q"))
(instance "AND2" (("hint_0n" 0) "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24w22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 2)
("sint_0n" 1)
("qint_0n" 1)
)
(instances
(instance "OR3" ("q" "i0" "i1" ("qint_0n" 0)))
(instance "OR3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("sint_0n" 0)))
(instance "AND2" (("sint_0n" 0) "i2" "i3"))
(instance "AND2" (("hint_0n" 1) "i3" "q"))
(instance "AND2" (("hint_0n" 0) "i2" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th33w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 1)
("qint_0n" 2)
)
(instances
(instance "OR2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "OR3" (("qint_0n" 2) ("sint_0n" 3) ("sint_0n" 4) ("sint_0n" 5)))
(instance "OR3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "AND2" (("qint_0n" 1) "i0" ("sint_0n" 0)))
(instance "OR2" (("sint_0n" 0) "i1" "i2"))
(instance "OR3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th34"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 4)
("sint_0n" 2)
("qint_0n" 2)
("sinti_0n" 2)
)
(instances
(instance "OR2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "OR2" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1)))
(instance "AND3" (("sint_0n" 1) "i1" "i3" ("sinti_0n" 1)))
(instance "OR2" (("sinti_0n" 1) "i0" "i2"))
(instance "AND3" (("sint_0n" 0) "i0" "i2" ("sinti_0n" 0)))
(instance "OR2" (("sinti_0n" 0) "i1" "i3"))
(instance "OR4" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2) ("hint_0n" 3)))
(instance "AND2" (("hint_0n" 3) "i3" "q"))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th34w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q" ("mint_0n" 0) ("mint_0n" 1) "i0"))
(instance "OR3" (("mint_0n" 1) "i1" "i2" "i3"))
(instance "c3" (("mint_0n" 0) "i1" "i2" "i3"))
)
(attributes (cell-type "helper"))
)
(circuit "th34w22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "th23" ("q" ("mint_0n" 0) "i0" "i1"))
(instance "OR2" (("mint_0n" 0) "i2" "i3"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "OR3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
(instance "c2" ("q_1" "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
(instance "OR3" ("q_1" "GND" ("n3_0n" 0) "GND"))
(instance "c2" (("n3_0n" 0) "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "c2" ("q_1" "i0_1" "i1_1"))
(instance "th34w22" ("q_0" "i0_0" "i1_0" "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "c2" ("q_0" "i0_0" "i1_0"))
(instance "OR3" ("q_1" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("q_0" "GND" ("n3_0n" 0) "GND"))
(instance "c2" (("n3_0n" 0) "i0_0" "i1_0"))
(instance "OR3" ("q_1" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "th34w22" ("q_1" "i0_1" "i1_1" "i0_0" "i1_0"))
(instance "c2" ("q_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_nor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "c2" ("q_1" "i0_0" "i1_0"))
(instance "OR3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_nor2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "c2" ("q_1" "i0_0" "i1_0"))
(instance "th34w22" ("q_0" "i0_1" "i1_1" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR2" ("q_0" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "OR2" ("q_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_xor2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "th23w2" ("q_1" ("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "th23w2" ("q_0" ("n0_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2_bal" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2_bal" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2_ncl" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2_ncl" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21_bal" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2_bal" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21_ncl" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2_ncl" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_mux2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("s_0" input 1)
("s_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR2" ("q_0" ("n0_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "s_0" "i0_0"))
(instance "c2" (("n2_0n" 0) "s_1" "i1_0"))
(instance "OR2" ("q_1" ("n1_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n1_0n" 0) "s_0" "i0_1"))
(instance "c2" (("n3_0n" 0) "s_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_mux2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("s_0" input 1)
("s_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "th23w2" ("q_1" ("n1_0n" 0) "s_0" "i0_1"))
(instance "c2" (("n1_0n" 0) "s_1" "i1_1"))
(instance "th23w2" ("q_0" ("n0_0n" 0) "s_0" "i0_0"))
(instance "c2" (("n0_0n" 0) "s_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "OR3" ("co_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_0" ("n0_0n" 0) "co_1"))
(instance "c2" ("co_1" "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("co_1" "GND" ("n3_0n" 0) "GND"))
(instance "OR3" ("co_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_0" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha_ncl"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
)
(instances
(instance "th23w2" ("co_0" "sum_1" "a_0" "b_0"))
(instance "th23w2" ("sum_1" ("n0_0n" 0) "a_1" "b_0"))
(instance "c2" (("n0_0n" 0) "a_0" "b_1"))
(instance "th23w2" ("sum_0" "co_1" "a_0" "b_0"))
(instance "c2" ("co_1" "a_1" "b_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("ha__1_0n" 1)
("ha__0_0n" 1)
("n0__1_0n" 1)
("n0_0n" 1)
)
(instances
(instance "th23w2" ("co_0" "sum_1" "a_0" "b_0"))
(instance "th23w2" ("sum_1" ("n0_0n" 0) "a_1" "b_0"))
(instance "c2" (("n0_0n" 0) "a_0" "b_1"))
(instance "th23w2" ("sum_0" "co_1" "a_0" "b_0"))
(instance "c2" ("co_1" "a_1" "b_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("ha__1_0n" 1)
("ha__0_0n" 1)
("n0__1_0n" 1)
("n0__0_0n" 1)
("n1__1_0n" 1)
("n1__0_0n" 1)
)
(instances
(instance "dr_xor2" (("n0__0_0n" 0) ("n0__1_0n" 0) ("n1__0_0n" 0) ("n1__1_0n" 0) "co_0" "co_1"))
(instance "dr_ha_bal" (("ha__0_0n" 0) ("ha__1_0n" 0) "ci_0" "ci_1" ("n1__0_0n" 0) ("n1__1_0n" 0) "sum_0" "sum_1"))
(instance "dr_ha_bal" ("a_0" "a_1" "b_0" "b_1" ("n0__0_0n" 0) ("n0__1_0n" 0) ("ha__0_0n" 0) ("ha__1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_fa"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("minterm_0n" 8)
)
(instances
(instance "OR4" ("co0" ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4)))
(instance "OR4" ("co1" ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 7)))
(instance "OR4" ("sum0" ("minterm_0n" 0) ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "OR4" ("sum1" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4) ("minterm_0n" 7)))
(instance "c3" (("minterm_0n" 7) "a1" "b1" "ci1"))
(instance "c3" (("minterm_0n" 6) "a1" "b1" "ci0"))
(instance "c3" (("minterm_0n" 5) "a1" "b0" "ci1"))
(instance "c3" (("minterm_0n" 4) "a1" "b0" "ci0"))
(instance "c3" (("minterm_0n" 3) "a0" "b1" "ci1"))
(instance "c3" (("minterm_0n" 2) "a0" "b1" "ci0"))
(instance "c3" (("minterm_0n" 1) "a0" "b0" "ci1"))
(instance "c3" (("minterm_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_fa"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
)
(instances
(instance "th34w2" ("sum1" "co0" "a1" "b1" "ci1"))
(instance "th34w2" ("sum0" "co1" "a0" "b0" "ci0"))
(instance "th23" ("co1" "a1" "b1" "ci1"))
(instance "th23" ("co0" "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("co_1" ("n1_0n" 0) ("n2_0n" 0) ("n3_0n" 0)))
(instance "OR2" ("sum_0" ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_1" "co_0" ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" ("co_0" "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("co_0" "GND" ("n0_0n" 0) "GND"))
(instance "OR3" ("co_1" ("n1_0n" 0) ("n2_0n" 0) ("n3_0n" 0)))
(instance "OR2" ("sum_0" ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_1" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p_ncl"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "th23w2" ("co_1" "sum_0" "a_0" "b_1"))
(instance "th23w2" ("sum_1" "co_0" "a_1" "b_1"))
(instance "c2" ("co_0" "a_0" "b_0"))
(instance "th23w2" ("sum_0" ("n0_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_1" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_fs"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("minterm_0n" 8)
)
(instances
(instance "OR4" ("co1" ("minterm_0n" 0) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "OR4" ("co0" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3) ("minterm_0n" 7)))
(instance "OR4" ("sum1" ("minterm_0n" 0) ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "OR4" ("sum0" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4) ("minterm_0n" 7)))
(instance "c3" (("minterm_0n" 7) "a1" "b1" "ci1"))
(instance "c3" (("minterm_0n" 6) "a1" "b1" "ci0"))
(instance "c3" (("minterm_0n" 5) "a1" "b0" "ci1"))
(instance "c3" (("minterm_0n" 4) "a1" "b0" "ci0"))
(instance "c3" (("minterm_0n" 3) "a0" "b1" "ci1"))
(instance "c3" (("minterm_0n" 2) "a0" "b1" "ci0"))
(instance "c3" (("minterm_0n" 1) "a0" "b0" "ci1"))
(instance "c3" (("minterm_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_fs"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("cint_0n" 2)
)
(instances
(instance "th23" ("co1" ("cint_0n" 0) "b1" ("ci1_0n" 0)))
(instance "th23" ("co0" ("cint_0n" 1) "b0" ("ci0_0n" 0)))
(instance "th34w2" ("sum1" ("cint_0n" 0) "a1" "b1" "ci1"))
(instance "th34w2" ("sum0" ("cint_0n" 1) "a0" "b0" "ci0"))
(instance "th23" (("cint_0n" 1) "a1" "b1" "ci1"))
(instance "th23" (("cint_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ha"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 4)
)
(instances
(instance "OR3" ("co_1" ("sopint_0n" 0) ("sopint_0n" 2) ("mint_0n" 11)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 3) "sum_3"))
(instance "OR4" ("sum_3" ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR2" ("sum_2" ("sopint_0n" 3) ("mint_0n" 11)))
(instance "OR2" ("sum_1" ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "OR2" ("sum_0" ("mint_0n" 0) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 3) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 10)))
(instance "OR2" (("sopint_0n" 2) ("mint_0n" 6) ("mint_0n" 7)))
(instance "OR2" (("sopint_0n" 1) ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 14) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 13) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 12) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 11) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 9) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 6) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "OR2" ("sum_3" ("mint_0n" 5) ("mint_0n" 6)))
(instance "OR2" ("sum_2" ("mint_0n" 3) ("mint_0n" 4)))
(instance "OR2" ("sum_1" ("mint_0n" 1) ("mint_0n" 2)))
(instance "OR2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 4)
)
(instances
(instance "OR4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "th23w2" ("sum_3" ("mint_0n" 3) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_1"))
(instance "th23w2" ("sum_2" ("mint_0n" 2) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "OR2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR2" ("s_1" ("mint_0n" 4) "sum_3"))
(instance "OR4" ("s_0" ("mint_0n" 0) "sum_1" ("mint_0n" 3) "co_1"))
(instance "OR4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "OR2" ("sum_3" ("mint_0n" 5) ("mint_0n" 6)))
(instance "OR2" ("sum_2" ("mint_0n" 3) ("mint_0n" 4)))
(instance "OR2" ("sum_1" ("mint_0n" 1) ("mint_0n" 2)))
(instance "OR2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR2" ("s_1" ("mint_0n" 3) "sum_3"))
(instance "OR4" ("s_0" ("mint_0n" 0) "sum_1" ("mint_0n" 2) "co_1"))
(instance "OR4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "th23w2" ("sum_3" ("mint_0n" 4) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "OR2" ("sum_2" ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "OR2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("halfsum_0n" 4)
("halfcar_0n" 4)
)
(instances
(instance "dr_xor2" (("halfcar_0n" 0) ("halfcar_0n" 1) ("halfcar_0n" 2) ("halfcar_0n" 3) "co_0" "co_1"))
(instance "oof_dims_ca" (("halfsum_0n" 0) ("halfsum_0n" 1) ("halfsum_0n" 2) ("halfsum_0n" 3) "ci_0" "ci_1" ("halfcar_0n" 2) ("halfcar_0n" 3) "sum_0" "sum_1" "sum_2" "sum_3"))
(instance "oof_ha" ("i0_0" "i0_1" "i0_2" "i0_3" "i1_0" "i1_1" "i1_2" "i1_3" ("halfcar_0n" 0) ("halfcar_0n" 1) ("halfsum_0n" 0) ("halfsum_0n" 1) ("halfsum_0n" 2) ("halfsum_0n" 3)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
)
(instances
(instance "OR4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "OR4" (("carrint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "OR4" (("carrint_0n" 6) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "OR4" (("carrint_0n" 5) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 21) ("minterm_0n" 22)))
(instance "OR4" (("carrint_0n" 4) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "OR4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "OR4" (("carrint_0n" 3) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24)))
(instance "OR4" (("carrint_0n" 2) ("minterm_0n" 9) ("minterm_0n" 10) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR4" (("carrint_0n" 1) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8)))
(instance "OR4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "OR2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "OR4" (("sumint_0n" 7) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "OR4" (("sumint_0n" 6) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "OR4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "OR4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "OR2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "OR4" (("sumint_0n" 3) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "OR4" (("sumint_0n" 2) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "OR2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "OR4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "OR4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fa_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
("overint_0n" 8)
)
(instances
(instance "OR4" ("s_1" ("overint_0n" 4) ("overint_0n" 5) ("overint_0n" 6) ("overint_0n" 7)))
(instance "OR4" (("overint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "OR4" (("overint_0n" 6) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 23) ("minterm_0n" 24)))
(instance "OR4" (("overint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 20)))
(instance "OR4" (("overint_0n" 4) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 12)))
(instance "OR4" ("s_0" ("overint_0n" 0) ("overint_0n" 1) ("overint_0n" 2) ("overint_0n" 3)))
(instance "OR4" (("overint_0n" 3) ("minterm_0n" 19) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "OR4" (("overint_0n" 2) ("minterm_0n" 11) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "OR4" (("overint_0n" 1) ("minterm_0n" 7) ("minterm_0n" 8) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "OR4" (("overint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "OR4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "OR4" (("carrint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "OR4" (("carrint_0n" 6) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "OR4" (("carrint_0n" 5) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 21) ("minterm_0n" 22)))
(instance "OR4" (("carrint_0n" 4) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "OR4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "OR4" (("carrint_0n" 3) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24)))
(instance "OR4" (("carrint_0n" 2) ("minterm_0n" 9) ("minterm_0n" 10) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR4" (("carrint_0n" 1) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8)))
(instance "OR4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "OR2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "OR4" (("sumint_0n" 7) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "OR4" (("sumint_0n" 6) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "OR4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "OR4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "OR2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "OR4" (("sumint_0n" 3) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "OR4" (("sumint_0n" 2) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "OR2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "OR4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "OR4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fs"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
)
(instances
(instance "OR4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "OR4" (("carrint_0n" 7) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 23) ("minterm_0n" 31)))
(instance "OR4" (("carrint_0n" 6) ("minterm_0n" 12) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "OR4" (("carrint_0n" 5) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 7) ("minterm_0n" 11)))
(instance "OR4" (("carrint_0n" 4) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3) ("minterm_0n" 4)))
(instance "OR4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "OR4" (("carrint_0n" 3) ("minterm_0n" 27) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "OR4" (("carrint_0n" 2) ("minterm_0n" 20) ("minterm_0n" 24) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "OR4" (("carrint_0n" 1) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 19)))
(instance "OR4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 8) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "OR2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "OR4" (("sumint_0n" 7) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "OR4" (("sumint_0n" 6) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "OR4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "OR4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "OR2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "OR4" (("sumint_0n" 3) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "OR4" (("sumint_0n" 2) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "OR2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "OR4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "OR4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 6)
("assoc_0n" 6)
("eqv_0n" 4)
("fsum_0n" 4)
("fcar_0n" 2)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 0)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 1)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 0)))
(instance "OR4" (("fcar_0n" 1) ("assoc_0n" 4) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "OR4" (("fcar_0n" 0) ("assoc_0n" 0) ("assoc_0n" 1) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "OR3" (("fsum_0n" 3) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 2)))
(instance "OR3" (("fsum_0n" 2) ("assoc_0n" 1) ("eqv_0n" 1) ("eqv_0n" 3)))
(instance "OR2" (("fsum_0n" 1) ("assoc_0n" 0) ("assoc_0n" 5)))
(instance "OR2" (("fsum_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "c2" (("eqv_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("eqv_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("eqv_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("eqv_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" (("assoc_0n" 5) ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23w2" (("assoc_0n" 4) ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23w2" (("assoc_0n" 3) ("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("assoc_0n" 2) ("mint_0n" 2) "i0_3" "i1_0"))
(instance "th23w2" (("assoc_0n" 1) ("mint_0n" 1) "i0_2" "i1_0"))
(instance "th23w2" (("assoc_0n" 0) ("mint_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fa_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 6)
("assoc_0n" 6)
("eqv_0n" 4)
("fsum_0n" 4)
("fcar_0n" 2)
("fext_0n" 2)
("fshar_0n" 1)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("s_1" ("fext_0n" 1) "ci_0" "ci_1" ("fshar_0n" 0)))
(instance "th34w22" ("s_0" ("fext_0n" 0) "ci_1" "ci_0" ("fshar_0n" 0)))
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 0)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 1)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 0)))
(instance "OR2" (("fshar_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "OR4" (("fext_0n" 1) ("assoc_0n" 1) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "OR4" (("fext_0n" 0) ("assoc_0n" 0) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "OR4" (("fcar_0n" 1) ("assoc_0n" 4) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "OR4" (("fcar_0n" 0) ("assoc_0n" 0) ("assoc_0n" 1) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "OR3" (("fsum_0n" 3) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 2)))
(instance "OR3" (("fsum_0n" 2) ("assoc_0n" 1) ("eqv_0n" 1) ("eqv_0n" 3)))
(instance "OR2" (("fsum_0n" 1) ("assoc_0n" 0) ("assoc_0n" 5)))
(instance "OR2" (("fsum_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "c2" (("eqv_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("eqv_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("eqv_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("eqv_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" (("assoc_0n" 5) ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23w2" (("assoc_0n" 4) ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23w2" (("assoc_0n" 3) ("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("assoc_0n" 2) ("mint_0n" 2) "i0_3" "i1_0"))
(instance "th23w2" (("assoc_0n" 1) ("mint_0n" 1) "i0_2" "i1_0"))
(instance "th23w2" (("assoc_0n" 0) ("mint_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fs"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("fsum_0n" 4)
("fcar_0n" 2)
("cint_0n" 2)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 3)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 0)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 0)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 1)))
(instance "OR3" (("fcar_0n" 1) ("mint_0n" 7) ("mint_0n" 11) ("cint_0n" 1)))
(instance "OR3" (("fcar_0n" 0) ("mint_0n" 13) ("mint_0n" 14) ("cint_0n" 0)))
(instance "OR4" (("cint_0n" 1) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "OR4" (("cint_0n" 0) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "OR4" (("fsum_0n" 3) ("mint_0n" 1) ("mint_0n" 6) ("mint_0n" 11) ("mint_0n" 12)))
(instance "OR4" (("fsum_0n" 2) ("mint_0n" 2) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 13)))
(instance "OR4" (("fsum_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 9) ("mint_0n" 14)))
(instance "OR4" (("fsum_0n" 0) ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 6)))
(instance "OR2" ("sum_3" "co_0" ("mint_0n" 6)))
(instance "OR2" ("sum_2" ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR2" ("sum_1" ("mint_0n" 2) ("mint_0n" 3)))
(instance "OR2" ("sum_0" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 4)
)
(instances
(instance "OR4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 3)))
(instance "OR2" ("sum_3" "co_0" ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_3" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
(instance "th23w2" ("sum_2" ("mint_0n" 2) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_2" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_1"))
(instance "th23w2" ("sum_0" ("mint_0n" 0) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR3" ("s_1" "sum_3" "sum_2" ("mint_0n" 3)))
(instance "OR2" ("s_0" "sum_0" ("mint_0n" 2)))
(instance "OR4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 6)))
(instance "OR2" ("sum_3" "co_0" ("mint_0n" 6)))
(instance "OR2" ("sum_2" ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR2" ("sum_1" ("mint_0n" 2) ("mint_0n" 3)))
(instance "OR2" ("sum_0" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 5)
)
(instances
(instance "OR3" ("s_1" "sum_3" "sum_2" ("mint_0n" 3)))
(instance "OR2" ("s_0" "sum_0" ("mint_0n" 2)))
(instance "OR4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 4)))
(instance "OR2" ("sum_3" "co_0" ("mint_0n" 4)))
(instance "c2" (("mint_0n" 4) "i0_3" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
(instance "OR2" ("sum_2" ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_2" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_1"))
(instance "th23w2" ("sum_0" ("mint_0n" 0) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 1)
)
(instances
(instance "OR4" ("co_1" ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("sopint_0n" 0) "sum_2" "sum_3"))
(instance "OR4" ("sum_3" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR4" ("sum_2" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "OR3" ("sum_1" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "OR3" ("sum_0" ("mint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 3)
("sumint_0n" 6)
("carint_0n" 5)
)
(instances
(instance "th23w2" ("co_1" ("carint_0n" 3) ("carint_0n" 4) "ci_1"))
(instance "OR3" (("carint_0n" 4) ("mint_0n" 0) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("carint_0n" 3) ("mint_0n" 0) "ci_0"))
(instance "OR3" ("co_0" ("carint_0n" 2) "sum_2" "sum_3"))
(instance "th23w2" (("carint_0n" 2) ("carint_0n" 1) ("carint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 1) ("carint_0n" 0) ("sopint_0n" 1) "ci_0"))
(instance "c2" (("carint_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 4) ("sumint_0n" 5) "ci_0"))
(instance "OR2" (("sumint_0n" 5) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("sumint_0n" 4) ("sopint_0n" 2) "ci_1"))
(instance "th23w2" ("sum_2" ("sumint_0n" 3) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sumint_0n" 2) "ci_1"))
(instance "OR2" (("sumint_0n" 2) ("sopint_0n" 0) ("mint_0n" 3)))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("mint_0n" 4) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 0) "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 2) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_3" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR2" ("s_1" ("sopint_0n" 2) ("mint_0n" 8)))
(instance "OR4" ("s_0" "sum_1" "sum_0" ("sopint_0n" 1) ("mint_0n" 7)))
(instance "OR4" ("co_1" ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("sopint_0n" 0) "sum_2" "sum_3"))
(instance "OR2" ("sum_3" ("mint_0n" 7) ("sopint_0n" 2)))
(instance "OR3" (("sopint_0n" 2) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR2" ("sum_2" ("sopint_0n" 1) ("mint_0n" 8)))
(instance "OR3" (("sopint_0n" 1) ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6)))
(instance "OR3" ("sum_1" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "OR3" ("sum_0" ("mint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 3)
("sumint_0n" 6)
("carint_0n" 5)
("exint_0n" 4)
)
(instances
(instance "th23w2" ("s_1" ("exint_0n" 3) ("mint_0n" 3) "ci_1"))
(instance "c2" (("exint_0n" 3) ("exint_0n" 2) "ci_0"))
(instance "OR3" (("exint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR3" ("s_0" "sum_1" "sum_0" ("exint_0n" 1)))
(instance "th23w2" (("exint_0n" 1) ("exint_0n" 0) ("mint_0n" 2) "ci_0"))
(instance "th23" (("exint_0n" 0) "ci_1" ("sopint_0n" 1) ("mint_0n" 2)))
(instance "th23w2" ("co_1" ("carint_0n" 3) ("carint_0n" 4) "ci_1"))
(instance "OR3" (("carint_0n" 4) ("mint_0n" 0) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("carint_0n" 3) ("mint_0n" 0) "ci_0"))
(instance "OR3" ("co_0" ("carint_0n" 2) "sum_2" "sum_3"))
(instance "th23w2" (("carint_0n" 2) ("carint_0n" 1) ("carint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 1) ("carint_0n" 0) ("sopint_0n" 1) "ci_0"))
(instance "c2" (("carint_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 4) ("sumint_0n" 5) "ci_0"))
(instance "OR2" (("sumint_0n" 5) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("sumint_0n" 4) ("sopint_0n" 2) "ci_1"))
(instance "th23w2" ("sum_2" ("sumint_0n" 3) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sumint_0n" 2) "ci_1"))
(instance "OR2" (("sumint_0n" 2) ("sopint_0n" 0) ("mint_0n" 4)))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("mint_0n" 5) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 0) "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "OR2" (("sopint_0n" 2) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_3" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 1)
)
(instances
(instance "OR3" ("co_1" ("sopint_0n" 0) "sum_0" "sum_1"))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "OR4" ("sum_3" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 15)))
(instance "OR4" ("sum_2" ("mint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" ("sum_1" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR4" ("sum_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 4)
("sumint_0n" 4)
("carint_0n" 2)
)
(instances
(instance "th23w2" ("co_1" ("carint_0n" 1) ("mint_0n" 1) "ci_0"))
(instance "th23" (("carint_0n" 1) ("sopint_0n" 3) ("mint_0n" 1) "ci_1"))
(instance "th23w2" ("co_0" ("carint_0n" 0) ("mint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 0) ("sopint_0n" 1) ("mint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_3" ("sumint_0n" 3) ("sopint_0n" 0) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_2" ("sumint_0n" 2) ("sopint_0n" 3) "ci_1"))
(instance "c2" (("sumint_0n" 2) ("sopint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sopint_0n" 2) "ci_1"))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 3) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 4) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "OR2" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("s_1" ("sopint_0n" 1) "sum_2" "sum_3"))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR4" ("s_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "OR3" ("co_1" ("sopint_0n" 0) "sum_0" "sum_1"))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "OR4" ("sum_3" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 15)))
(instance "OR4" ("sum_2" ("mint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" ("sum_1" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR4" ("sum_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 4)
("sumint_0n" 4)
("carint_0n" 2)
("exint_0n" 3)
)
(instances
(instance "OR3" ("s_1" "sum_2" "sum_3" ("exint_0n" 2)))
(instance "th23w2" (("exint_0n" 2) ("exint_0n" 1) ("mint_0n" 4) "ci_1"))
(instance "th23" (("exint_0n" 1) "ci_0" ("sopint_0n" 3) ("mint_0n" 4)))
(instance "th23w2" ("s_0" ("exint_0n" 0) ("mint_0n" 3) "ci_0"))
(instance "th23" (("exint_0n" 0) "ci_1" ("sopint_0n" 1) ("mint_0n" 3)))
(instance "th23w2" ("co_1" ("carint_0n" 1) ("mint_0n" 1) "ci_0"))
(instance "th23" (("carint_0n" 1) ("sopint_0n" 3) ("mint_0n" 1) "ci_1"))
(instance "th23w2" ("co_0" ("carint_0n" 0) ("mint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 0) ("sopint_0n" 1) ("mint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_3" ("sumint_0n" 3) ("sopint_0n" 0) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_2" ("sumint_0n" 2) ("sopint_0n" 3) "ci_1"))
(instance "c2" (("sumint_0n" 2) ("sopint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sopint_0n" 2) "ci_1"))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 3) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "OR2" (("sopint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "OR2" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 15)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("q0_2" ("mint_0n" 10) ("mint_0n" 11) ("mint_0n" 14)))
(instance "OR3" ("q0_1" ("mint_0n" 5) ("mint_0n" 7) ("mint_0n" 13)))
(instance "OR3" ("q0_0" ("mint_0n" 12) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 4) ("mint_0n" 6) ("mint_0n" 8) ("mint_0n" 9)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" ("q0_3" "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_3" "i0_3" "i1_3"))
(instance "th23w2" ("q0_2" ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23" (("mint_0n" 5) "i0_2" "i1_2" "i1_3"))
(instance "th23w2" ("q0_1" ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23" (("mint_0n" 4) "i0_1" "i1_1" "i1_3"))
(instance "th23w2" ("q0_0" ("sopint_0n" 0) "i0_3" "i1_0"))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_1" "i1_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_0" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 15)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("q0_3" ("mint_0n" 14) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 10) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "OR3" ("q0_2" ("mint_0n" 1) ("mint_0n" 7) ("mint_0n" 9)))
(instance "OR3" ("q0_1" ("mint_0n" 0) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 11) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 7) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
(instance "c2" ("q0_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_3" ("sopint_0n" 0) "i0_0" "i1_3"))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "th23" (("mint_0n" 5) "i0_3" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 4) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_1" "i1_3"))
(instance "th23" (("mint_0n" 2) "i0_1" "i1_2" "i1_3"))
(instance "th23w2" ("q0_2" ("mint_0n" 1) "i0_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_2"))
(instance "th23w2" ("q0_1" ("mint_0n" 0) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
(instance "c2" ("q0_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 16)
)
(instances
(instance "OR4" ("q0_3" ("mint_0n" 3) ("mint_0n" 6) ("mint_0n" 9) ("mint_0n" 12)))
(instance "OR4" ("q0_2" ("mint_0n" 2) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 13)))
(instance "OR4" ("q0_1" ("mint_0n" 1) ("mint_0n" 4) ("mint_0n" 11) ("mint_0n" 14)))
(instance "OR4" ("q0_0" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 8)
)
(instances
(instance "OR2" ("q0_3" ("sopint_0n" 6) ("sopint_0n" 7)))
(instance "th23w2" (("sopint_0n" 7) ("mint_0n" 7) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_2"))
(instance "th23w2" (("sopint_0n" 6) ("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 6) "i0_0" "i1_3"))
(instance "OR2" ("q0_2" ("sopint_0n" 4) ("sopint_0n" 5)))
(instance "th23w2" (("sopint_0n" 5) ("mint_0n" 5) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_3"))
(instance "th23w2" (("sopint_0n" 4) ("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_2"))
(instance "OR2" ("q0_1" ("sopint_0n" 2) ("sopint_0n" 3)))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 3) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_3"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "OR2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR4" ("q0_1" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "OR3" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "OR4" (("sopint_0n" 2) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 9)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 2)
)
(instances
(instance "OR2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 5) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 4) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_0"))
(instance "OR4" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th34w2" (("mint_0n" 3) "i0_3" "i1_1" "i1_1" "i1_2"))
(instance "th34w2" (("mint_0n" 2) "i0_2" "i1_0" "i1_1" "i1_3"))
(instance "th34w2" (("mint_0n" 1) "i0_1" "i1_0" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 0) "i0_0" "i1_1" "i1_2" "i1_3"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 0) ("mint_0n" 3)))
(instance "OR3" ("q0_0" ("mint_0n" 1) ("mint_0n" 2) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_1" ("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_0"))
(instance "OR2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_2" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR3" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "OR4" (("sopint_0n" 2) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 9)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "OR4" ("q0_0" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 2)
)
(instances
(instance "OR4" ("q0_1" ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "th34w2" (("mint_0n" 5) "i0_3" "i1_1" "i1_1" "i1_2"))
(instance "th34w2" (("mint_0n" 4) "i0_2" "i1_0" "i1_1" "i1_3"))
(instance "th34w2" (("mint_0n" 3) "i0_1" "i1_0" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 2) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "OR2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR3" ("q0_1" ("mint_0n" 1) ("mint_0n" 2) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "OR2" ("q0_0" ("mint_0n" 0) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 2)
)
(instances
(instance "OR2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("q0_2" ("sopint_0n" 1) ("mint_0n" 7) ("mint_0n" 11)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "OR4" ("q0_1" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "OR3" ("q0_0" ("sopint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("q0_2" ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 6) "i0_1" "i1_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "OR2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 4) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_0"))
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th34w2" (("mint_0n" 2) "i0_3" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 0) ("mint_0n" 2)))
(instance "OR2" ("q0_0" ("mint_0n" 6) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_0"))
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ineq_sgn_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 0) ("mint_0n" 2)))
(instance "OR2" ("q0_2" ("mint_0n" 6) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ineq_sgn_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "OR3" ("q0_2" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th23" (("mint_0n" 3) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR3" ("q0_1" ("sopint_0n" 2) ("mint_0n" 7) ("mint_0n" 11)))
(instance "OR4" (("sopint_0n" 2) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "OR4" ("q0_0" ("mint_0n" 14) ("mint_0n" 15) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12) ("mint_0n" 13)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 8)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR3" (("q0__1_0n" 0) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 6) "i0_1" "i1_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "OR3" ("q0_0" ("mint_0n" 3) ("mint_0n" 4) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 4) "i0_3" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 3) "i0_3" "i1_0" "i1_1"))
(instance "th34w2" (("mint_0n" 2) "i0_2" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_1" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR3" ("q0_1" ("sopint_0n" 2) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" (("sopint_0n" 2) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "OR4" ("q0_0" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 10)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR3" ("q0_1" ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_3" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 6) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_0"))
(instance "OR3" ("q0_0" ("mint_0n" 3) ("mint_0n" 4) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 4) "i0_3" "i1_3"))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 2) "i0_1" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 1) "i0_0" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "OR4" ("q0_0" ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "th23w2" ("q0_0" ("sopint_0n" 0) "i0_0" "i1_0"))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 7) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6)))
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_1" ("sopint_0n" 0) "i0_1" "i1_0"))
(instance "OR2" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
)
(instances
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_0" "i1_0"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" ("q0_1" "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_1" "i1_0"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_oot_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
)
(instances
(instance "OR3" ("q0_1" ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_oot_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q0_1" ("mint_0n" 1) "i0_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_1" "i1_1" "i1_2"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_0"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oot_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 9)
)
(instances
(instance "OR4" ("q0_2" ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "OR4" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 6) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_2"))
(instance "c2" ("q0_1" "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oot_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q0_2" ("mint_0n" 1) "i0_1" "i1_2"))
(instance "th34w2" (("mint_0n" 1) "i0_2" "i1_0" "i1_1" "i1_2"))
(instance "c2" ("q0_1" "i0_1" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_0"))
(instance "th34w2" (("mint_0n" 0) "i0_0" "i1_0" "i1_1" "i1_2"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
)
(instances
(instance "ao22" ("in_a" "in_0" "out_0" "in_1" "out_1"))
(instance "NOR2" ("out_0" "in_1" "out_1"))
(instance "NOR2" ("out_1" "in_0" "out_0"))
)
(attributes (simulation-initialise ("out_0" 1)) (cell-type "helper"))
)
(circuit "dr_spacer_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("phaseOne_0n" 2)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "OR2" ("in_a" ("phaseOne_0n" 0) ("phaseOne_0n" 1)))
(instance "OR2" (("outcomp_0n" 0) "out_0" "out_1"))
(instance "OR2" (("incomp_0n" 0) "in_0" "in_1"))
(instance "NOR3" ("out_1" ("incomp_0n" 0) ("phaseOne_0n" 1) "out_0"))
(instance "NOR3" ("out_0" ("incomp_0n" 0) ("phaseOne_0n" 0) "out_1"))
(instance "NOR3" (("phaseOne_0n" 1) ("outcomp_0n" 0) "in_1" ("phaseOne_0n" 0)))
(instance "NOR3" (("phaseOne_0n" 0) ("outcomp_0n" 0) "in_0" ("phaseOne_0n" 1)))
)
(attributes (simulation-initialise ("out_0" 1)) (cell-type "helper"))
)
(circuit "dr_ncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("phaseOne_0n" 2)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "OR2" ("in_a" ("phaseOne_0n" 0) ("phaseOne_0n" 1)))
(instance "NOR2" (("outcomp_0n" 0) "out_0" "out_1"))
(instance "NOR2" (("incomp_0n" 0) "in_0" "in_1"))
(instance "c2" ("out_1" ("phaseOne_0n" 1) ("incomp_0n" 0)))
(instance "c2" ("out_0" ("phaseOne_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("phaseOne_0n" 1) "in_1" ("outcomp_0n" 0)))
(instance "c2" (("phaseOne_0n" 0) "in_0" ("outcomp_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_tncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_r" input 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("writeSel_0n" 2)
("phaseOne_0n" 2)
("phaseTwo_0n" 2)
("readStore_0n" 2)
("wrcomp_0n" 1)
("incomp_0n" 1)
("pocomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "c2" ("in_a" ("pocomp_0n" 0) ("wrcomp_0n" 0)))
(instance "OR2" (("pocomp_0n" 0) ("phaseOne_0n" 0) ("phaseOne_0n" 1)))
(instance "NOR2" (("outcomp_0n" 0) ("phaseTwo_0n" 0) ("phaseTwo_0n" 1)))
(instance "NOR2" (("incomp_0n" 0) ("writeSel_0n" 0) ("writeSel_0n" 1)))
(instance "OR2" (("wrcomp_0n" 0) "in_0" "in_1"))
(instance "c2" ("out_1" ("readStore_0n" 1) ("pocomp_0n" 0)))
(instance "c2" ("out_0" ("readStore_0n" 0) ("pocomp_0n" 0)))
(instance "c2" (("readStore_0n" 1) ("phaseTwo_0n" 1) "out_r"))
(instance "c2" (("readStore_0n" 0) ("phaseTwo_0n" 0) "out_r"))
(instance "c2" (("phaseTwo_0n" 1) ("phaseOne_0n" 1) ("incomp_0n" 0)))
(instance "c2" (("phaseTwo_0n" 0) ("phaseOne_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("phaseOne_0n" 1) ("writeSel_0n" 1) ("outcomp_0n" 0)))
(instance "c2" (("phaseOne_0n" 0) ("writeSel_0n" 0) ("outcomp_0n" 0)))
(instance "OR2" (("writeSel_0n" 1) "in_1" ("readStore_0n" 1)))
(instance "OR2" (("writeSel_0n" 0) "in_0" ("readStore_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("inp__nor_0n" 4)
("cross__na_0n" 2)
("nor__latch_0n" 4)
("group__na_0n" 4)
("ack__na_0n" 2)
("ph__4_0n" 4)
)
(instances
(instance "OR2" ("in_a" ("ack__na_0n" 0) ("ack__na_0n" 1)))
(instance "NAND2" (("ack__na_0n" 1) ("group__na_0n" 2) ("group__na_0n" 3)))
(instance "NAND2" (("ack__na_0n" 0) ("group__na_0n" 0) ("group__na_0n" 1)))
(instance "NAND2" (("group__na_0n" 3) "in_3" ("nor__latch_0n" 3)))
(instance "NAND2" (("group__na_0n" 2) "in_2" ("nor__latch_0n" 2)))
(instance "NAND2" (("group__na_0n" 1) "in_1" ("nor__latch_0n" 1)))
(instance "NAND2" (("group__na_0n" 0) "in_0" ("nor__latch_0n" 0)))
(instance "NOR2" (("nor__latch_0n" 3) ("cross__na_0n" 0) "out_2"))
(instance "NOR2" (("nor__latch_0n" 2) ("cross__na_0n" 0) "out_3"))
(instance "NOR2" (("nor__latch_0n" 1) ("cross__na_0n" 1) "out_0"))
(instance "NOR2" (("nor__latch_0n" 0) ("cross__na_0n" 1) "out_1"))
(instance "NAND2" (("cross__na_0n" 1) ("inp__nor_0n" 2) ("inp__nor_0n" 3)))
(instance "NAND2" (("cross__na_0n" 0) ("inp__nor_0n" 0) ("inp__nor_0n" 1)))
(instance "INV" ("out_3" ("inp__nor_0n" 3)))
(instance "INV" ("out_2" ("inp__nor_0n" 2)))
(instance "INV" ("out_1" ("inp__nor_0n" 1)))
(instance "INV" ("out_0" ("inp__nor_0n" 0)))
(instance "NOR2" (("inp__nor_0n" 3) "in_3" ("nor__latch_0n" 3)))
(instance "NOR2" (("inp__nor_0n" 2) "in_2" ("nor__latch_0n" 2)))
(instance "NOR2" (("inp__nor_0n" 1) "in_1" ("nor__latch_0n" 1)))
(instance "NOR2" (("inp__nor_0n" 0) "in_0" ("nor__latch_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("PhaseOne_0n" 4)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "OR4" ("in_a" ("PhaseOne_0n" 0) ("PhaseOne_0n" 1) ("PhaseOne_0n" 2) ("PhaseOne_0n" 3)))
(instance "NOR4" (("outcomp_0n" 0) "out_0" "out_1" "out_2" "out_3"))
(instance "NOR4" (("incomp_0n" 0) "in_0" "in_1" "in_2" "in_3"))
(instance "c2" ("out_3" ("PhaseOne_0n" 3) ("incomp_0n" 0)))
(instance "c2" ("out_2" ("PhaseOne_0n" 2) ("incomp_0n" 0)))
(instance "c2" ("out_1" ("PhaseOne_0n" 1) ("incomp_0n" 0)))
(instance "c2" ("out_0" ("PhaseOne_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 3) "in_3" ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 2) "in_2" ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 1) "in_1" ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 0) "in_0" ("outcomp_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_tncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_r" input 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("WriteSel_0n" 4)
("PhaseOne_0n" 4)
("PhaseTwo_0n" 4)
("ReadStore_0n" 4)
("wrcomp_0n" 1)
("incomp_0n" 1)
("pocomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "c2" ("in_a" ("pocomp_0n" 0) ("wrcomp_0n" 0)))
(instance "OR4" (("pocomp_0n" 0) ("PhaseOne_0n" 0) ("PhaseOne_0n" 1) ("PhaseOne_0n" 2) ("PhaseOne_0n" 3)))
(instance "NOR4" (("outcomp_0n" 0) ("PhaseTwo_0n" 0) ("PhaseTwo_0n" 1) ("PhaseTwo_0n" 2) ("PhaseTwo_0n" 3)))
(instance "NOR4" (("incomp_0n" 0) ("WriteSel_0n" 0) ("WriteSel_0n" 1) ("WriteSel_0n" 2) ("WriteSel_0n" 3)))
(instance "OR4" (("wrcomp_0n" 0) "in_0" "in_1" "in_2" "in_3"))
(instance "c2" ("out_3" ("ReadStore_0n" 3) ("pocomp_0n" 0)))
(instance "c2" ("out_2" ("ReadStore_0n" 2) ("pocomp_0n" 0)))
(instance "c2" ("out_1" ("ReadStore_0n" 1) ("pocomp_0n" 0)))
(instance "c2" ("out_0" ("ReadStore_0n" 0) ("pocomp_0n" 0)))
(instance "c2" (("ReadStore_0n" 3) ("PhaseTwo_0n" 3) "out_r"))
(instance "c2" (("ReadStore_0n" 2) ("PhaseTwo_0n" 2) "out_r"))
(instance "c2" (("ReadStore_0n" 1) ("PhaseTwo_0n" 1) "out_r"))
(instance "c2" (("ReadStore_0n" 0) ("PhaseTwo_0n" 0) "out_r"))
(instance "c2" (("PhaseTwo_0n" 3) ("PhaseOne_0n" 3) ("incomp_0n" 0)))
(instance "c2" (("PhaseTwo_0n" 2) ("PhaseOne_0n" 2) ("incomp_0n" 0)))
(instance "c2" (("PhaseTwo_0n" 1) ("PhaseOne_0n" 1) ("incomp_0n" 0)))
(instance "c2" (("PhaseTwo_0n" 0) ("PhaseOne_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 3) ("WriteSel_0n" 3) ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 2) ("WriteSel_0n" 2) ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 1) ("WriteSel_0n" 1) ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 0) ("WriteSel_0n" 0) ("outcomp_0n" 0)))
(instance "OR2" (("WriteSel_0n" 3) "in_3" ("ReadStore_0n" 3)))
(instance "OR2" (("WriteSel_0n" 2) "in_2" ("ReadStore_0n" 2)))
(instance "OR2" (("WriteSel_0n" 1) "in_1" ("ReadStore_0n" 1)))
(instance "OR2" (("WriteSel_0n" 0) "in_0" ("ReadStore_0n" 0)))
)
(attributes (cell-type "helper"))
)
balsa-tech-xilinx/xilinx/.svn/0000755003172000014400000000000010212061546016541 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/text-base/0000755003172000014400000000000010212061546020435 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/text-base/gate-mappings.svn-base0000444003172000014400000002757610212061546024650 0ustar tomswapt00000000000000;;;
;;; `gate-mappings'
;;; Abstract->concrete gate mappings, for Xilinx 'Generic' technology
;;;
;;; 05 Mar 2004, Sam Taylor
;;; 02 Jul 1999, Andrew Bardsley
;;;
;;; This file has lists of (abs-gate-name default-real-gate . weighted-real-gates)
;;; The default real gate is used where nodal load management is not used and has the form:
;;; (gate-name . pin-mappings)
;;; The weighted-real-gates have the form:
;;; (output-drive gate-name . pin-mappings)
;;; The pin-mappings are lists of integers mapping abstract gate pin numbers to real gate pin
;;; numbers. The integers correspond to abstract gate pin positions (0 based) and their position
;;; to the position of that pin in the real gate. eg.
;;; (0 "q1and2d0" 2 1 0) is a drive 0 2-input and gate where pin 2 of the abstract gate (in2) is
;;; pin 0 of the real gate.
;;; and{n}: out,in1,in2...
("and2" ("and2" 0 1 2) (1 "and2"))
("and3" ("and3" 0 1 2 3) (1 "and3"))
("and4" ("and4" 0 1 2 3 4) (1 "and4"))
("and5" ("and5" 0 1 2 3 4 5) (1 "and5"))
;;; nand{n}: out,in1,in2...
("nand2" ("nand2" 0 1 2) (1 "nand2"))
("nand3" ("nand3" 0 1 2 3) (1 "nand3"))
("nand4" ("nand4" 0 1 2 3 4) (1 "nand4"))
("nand5" ("nand5" 0 1 2 3 4 5) (1 "nand5"))
;;; or{n}: out,in1,in2...
("or2" ("or2" 0 1 2) (1 "or2"))
("or3" ("or3" 0 1 2 3) (1 "or3"))
("or4" ("or4" 0 1 2 3 4) (1 "or4"))
("or5" ("or5" 0 1 2 3 4 5) (1 "or5"))
;;; nor{n}: out,in1,in2...
("nor2" ("nor2" 0 1 2) (1 "nor2"))
("nor3" ("nor3" 0 1 2 3) (1 "nor3"))
("nor4" ("nor4" 0 1 2 3 4) (1 "nor4"))
("nor5" ("nor5" 0 1 2 3 4 5) (1 "nor5"))
;;; xor2: out,in1,in2
("xor2" ("xor2" 0 1 2) (1 "xor2"))
;;; xnor2: out,in1,in2
("xnor2" ("xnor2" 0 1 2) (1 "xnor2"))
;;; inv: out,in
("inv" ("inv" 0 1) (1 "inv"))
;;; NB. buf is a driving buffer not a logical buffer
;;; buf: out,in
("buf" ("buff" 0 1) (1 "buff") (2 "BU2") (3 "BU3") (4 "BU4") (8 "BU8"))
("suggested-buffer" ("buff" 0 1) (1 "buff"))
;;; NB. connect is a logical buffer
;;; connect: out,in
("connect" ("buff" 0 1) (1 "buff"))
;;; latch: in,out,enable
("latch" ("fd" 2 0 1) (1 "fd"))
;;; Edge Triggered Flip Flop with async clear
("edge-dff-clr" ("fdc" 3 1 2 0) (1 "fdc"))
("adder" ("balsa_fa" 0 1 2 3 4 5 6 7) (1 "balsa_fa"))
;;; mutex: inA,inB,outA,outB
;;; mutual exclusion unit
("mutex" ("mutex1" 2 3 0 1) (1 "mutex1"))
;;; Helper Cells
("and-or22" ("ao22" 0 1 2 3 4) (1 "ao22"))
("and-or-invert22" ("aoi22" 0 1 2 3 4) (1 "aoi22"))
("and-or222" ("ao222" 0 1 2 3 4 5 6) (1 "ao222"))
("and-or-invert222" ("aoi222" 0 1 2 3 4 5 6) (1 "aoi222"))
("set-reset-flip-flop" ("srff" 0 1 2 3) (1 "srff"))
("mux2" ("mux2" 0 1 2 3) (1 "mux2"))
("nmux2" ("nmux2" 0 1 2 3) (1 "nmux2"))
("single-rail-full-adder" ("balsa_fa" 0 1 2 3 4 5 6 7) (1 "balsa_fa"))
("c-element2" ("c2" 0 1 2) (1 "c2"))
("c-element3" ("c3" 0 1 2 3) (1 "c3"))
("inverted-c-element" ("nc2" 0 1 2) (1 "nc2"))
("inverted-assym-c-element" ("nc2p" 0 1 2) (1 "nc2p"))
("demux2" ("demux2" 0 1 2 3) (1 "demux2"))
("s-element" ("selem" 0 1 2 3) (1 "selem"))
("th22" ("th22" 0 1 2) (1 "th22"))
("th33" ("th33" 0 1 2 3) (1 "th33"))
("th23" ("th23" 0 1 2 3) (1 "th23"))
("th23w2" ("th23w2" 0 1 2 3) (1 "th23w2"))
("th24" ("th24" 0 1 2 3 4) (1 "th24"))
("th24w2" ("th24w2" 0 1 2 3 4) (1 "th24w2"))
("th24w22" ("th24w22" 0 1 2 3 4) (1 "th24w22"))
("th33w2" ("th33w2" 0 1 2 3) (1 "th33w2"))
("th34" ("th34" 0 1 2 3 4) (1 "th34"))
("th34w2" ("th34w2" 0 1 2 3 4) (1 "th34w2"))
("th34w22" ("th34w22" 0 1 2 3 4) (1 "th34w22"))
("dual-rail-and2" ("dr_and2" 0 1 2 3 4 5) (1 "dr_and2"))
("dual-rail-and2-bal" ("dr_and2_bal" 0 1 2 3 4 5) (1 "dr_and2_bal"))
("dual-rail-and2-ncl" ("dr_and2_ncl" 0 1 2 3 4 5) (1 "dr_and2_ncl"))
("dual-rail-or2" ("dr_or2" 0 1 2 3 4 5) (1 "dr_or2"))
("dual-rail-or2-bal" ("dr_or2_bal" 0 1 2 3 4 5) (1 "dr_or2_bal"))
("dual-rail-or2-ncl" ("dr_or2_ncl" 0 1 2 3 4 5) (1 "dr_or2_ncl"))
("dual-rail-nor2" ("dr_nor2" 0 1 2 3 4 5) (1 "dr_nor2"))
("dual-rail-nor2-ncl" ("dr_nor2_ncl" 0 1 2 3 4 5) (1 "dr_nor2_ncl"))
("dual-rail-xor2" ("dr_xor2" 0 1 2 3 4 5) (1 "dr_xor2"))
("dual-rail-xor2-ncl" ("dr_xor2_ncl" 0 1 2 3 4 5) (1 "dr_xor2_ncl"))
("dual-rail-ao21" ("dr_ao21" 0 1 2 3 4 5 6 7) (1 "dr_ao21"))
("dual-rail-ao21-bal" ("dr_ao21_bal" 0 1 2 3 4 5 6 7) (1 "dr_ao21_bal"))
("dual-rail-ao21-ncl" ("dr_ao21_ncl" 0 1 2 3 4 5 6 7) (1 "dr_ao21_ncl"))
("dual-rail-ineq-comp" ("dr_ineq_comp" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp"))
("dual-rail-ineq-comp-bal" ("dr_ineq_comp_bal" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp_bal"))
("dual-rail-ineq-comp-ncl" ("dr_ineq_comp_ncl" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp_ncl"))
("dual-rail-mux2" ("dr_mux2" 0 1 2 3 4 5 6 7) (1 "dr_mux2"))
("dual-rail-mux2-ncl" ("dr_mux2_ncl" 0 1 2 3 4 5 6 7) (1 "dr_mux2_ncl"))
("dual-rail-half-adder" ("dr_ha" 0 1 2 3 4 5 6 7) (1 "dr_ha"))
("dual-rail-half-adder-bal" ("dr_ha_bal" 0 1 2 3 4 5 6 7) (1 "dr_ha_bal"))
("dual-rail-half-adder-ncl" ("dr_ha_ncl" 0 1 2 3 4 5 6 7) (1 "dr_ha_ncl"))
("dual-rail-full-adder" ("dr_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_fa"))
("dual-rail-full-adder-bal" ("dr_fa_bal" 0 1 2 3 4 5 6 7 8 9) (1 "dr_fa_bal"))
("dual-rail-dims-adder" ("dr_dims_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_dims_fa"))
("dual-rail-ncl-adder" ("dr_ncl_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_ncl_fa"))
("dual-rail-full-adder-primed" ("dr_fa_p" 0 1 2 3 4 5 6 7) (1 "dr_fa_p"))
("dual-rail-full-adder-primed-bal" ("dr_fa_p_bal" 0 1 2 3 4 5 6 7) (1 "dr_fa_p_bal"))
("dual-rail-full-adder-primed-ncl" ("dr_fa_p_ncl" 0 1 2 3 4 5 6 7) (1 "dr_fa_p_ncl"))
("dual-rail-dims-subtracter" ("dr_dims_fs" 0 1 2 3 4 5 6 7 8 9) (1 "dr_dims_fs"))
("dual-rail-ncl-subtracter" ("dr_ncl_fs" 0 1 2 3 4 5 6 7 8 9) (1 "dr_ncl_fs"))
("one-of-four-half-adder" ("oof_ha" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ha"))
("one-of-four-dims-carry-adder" ("oof_dims_ca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_ca"))
("one-of-four-ncl-carry-adder" ("oof_ncl_ca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_ca"))
("oof_dims_ca_se" ("oof_dims_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dims_ca_se"))
("one-of-four-dims-carry-adder-overflow" ("oof_ncl_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ncl_ca_se"))
("one-of-four-full-adder" ("oof_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_fa"))
("one-of-four-dims-full-adder" ("oof_dims_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dims_fa"))
("one-of-four-dims-full-adder-overflow" ("oof_dims_fa_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17) (1 "oof_dims_fa_se"))
("one-of-four-dims-subtracter" ("oof_dims_fs" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dims_fs"))
("one-of-four-ncl-full-adder" ("oof_ncl_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_ncl_fa"))
("one-of-four-ncl-full-adder-overflow" ("oof_ncl_fa_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17) (1 "oof_ncl_fa_se"))
("one-of-four-ncl-subtracter" ("oof_ncl_fs" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_ncl_fs"))
("one-of-four-dims-primed-carry-adder" ("oof_dims_pca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_pca"))
("one-of-four-ncl-primed-carry-adder" ("oof_ncl_pca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_pca"))
("one-of-four-dims-primed-carry-adder-overflow" ("oof_dims_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dims_pca_se"))
("one-of-four-ncl-primed-carry-adder-overflow" ("oof_ncl_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ncl_pca_se"))
("one-of-four-dual-rail-dims-carry-adder" ("oof_dr_dims_ca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_dims_ca"))
("one-of-four-dual-rail-ncl-carry-adder" ("oof_dr_ncl_ca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_ncl_ca"))
("one-of-four-dual-rail-dims-carry-adder-overflow" ("oof_dr_dims_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_dims_ca_se"))
("one-of-four-dual-rail-ncl-carry-adder-overflow" ("oof_dr_ncl_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_ncl_ca_se"))
("one-of-four-dual-rail-dims-primed-carry-adder" ("oof_dr_dims_pca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_dims_pca"))
("one-of-four-dual-rail-ncl-primed-carry-adder" ("oof_dr_ncl_pca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_ncl_pca"))
("one-of-four-dual-rail-dims-primed-carry-adder-overflow" ("oof_dr_dims_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_dims_pca_se"))
("one-of-four-dual-rail--ncl-primed-carry-adder-overflow" ("oof_dr_ncl_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_ncl_pca_se"))
("one-of-four-dims-and2" ("oof_dims_and2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_and2"))
("one-of-four-ncl-and2" ("oof_ncl_and2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_and2"))
("one-of-four-dims-or2" ("oof_dims_or2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_or2"))
("one-of-four-ncl-or2" ("oof_ncl_or2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_or2"))
("one-of-four-dims-xor2" ("oof_dims_xor2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_xor2"))
("one-of-four-ncl-xor2" ("oof_ncl_xor2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_xor2"))
("oof_dims_equal" ("oof_dims_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_equal"))
("oof_ncl_equal" ("oof_ncl_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_equal"))
("oof_dr_dims_equal" ("oof_dr_dims_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dr_dims_equal"))
("oof_dr_ncl_equal" ("oof_dr_ncl_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dr_ncl_equal"))
("one-of-four-dims-inequal" ("oof_dims_inequal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_inequal"))
("one-of-four-ncl-inequal" ("oof_ncl_inequal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_inequal"))
("oof_dr_dims_inequal" ("oof_dr_dims_inequal" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_inequal"))
("one-of-four-dual-rail-ncl-inequal" ("oof_dr_ncl_inequal" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_inequal"))
("one-of-four-dims-comp" ("oof_dims_comp" 0 1 2 3 4 5 6 7 8 9 10) (1 "oof_dims_comp"))
("one-of-four-ncl-comp" ("oof_ncl_comp" 0 1 2 3 4 5 6 7 8 9 10) (1 "oof_ncl_comp"))
("oof_dr_dims_ineq_comp" ("oof_dr_dims_ineq_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_dims_ineq_comp"))
("oof_dr_ncl_ineq_comp" ("oof_dr_ncl_ineq_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_ncl_ineq_comp"))
("oof_dr_dims_ineq_sgn_comp" ("oof_dr_dims_ineq_sgn_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_dims_ineq_sgn_comp"))
("oof_dr_ncl_ineq_sgn_comp" ("oof_dr_ncl_ineq_sgn_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_ncl_ineq_sgn_comp"))
("one-of-four-dims-less-than" ("oof_dims_lt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_lt"))
("one-of-four-ncl-less-than" ("oof_ncl_lt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_lt"))
("one-of-four-dims-greater-than" ("oof_dims_gt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_gt"))
("one-of-four-ncl-greater-than" ("oof_ncl_gt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_gt"))
("one-of-four-dual-rail-dims-less-than" ("oof_dr_dims_lt" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_lt"))
("one-of-four-dual-rail-ncl-less-than" ("oof_dr_ncl_lt" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_lt"))
("one-of-four-dual-rail-dims-greater-than" ("oof_dr_dims_gt" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_gt"))
("one-of-four-dual-rail-ncl-greater-than" ("oof_dr_ncl_gt" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_gt"))
("dual-rail-dims-comp" ("dr_dims_comp" 0 1 2 3 4 5 6) (1 "dr_dims_comp"))
("dual-rail-ncl-comp" ("dr_ncl_comp" 0 1 2 3 4 5 6) (1 "dr_ncl_comp"))
("dual-rail-dims-less-than" ("dr_dims_lt" 0 1 2 3 4 5) (1 "dr_dims_lt"))
("dual-rail-ncl-less-than" ("dr_ncl_lt" 0 1 2 3 4 5) (1 "dr_ncl_lt"))
("dual-rail-dims-greater-than" ("dr_dims_gt" 0 1 2 3 4 5) (1 "dr_dims_gt"))
("dual-rail-ncl-greater-than" ("dr_ncl_gt" 0 1 2 3 4 5) (1 "dr_ncl_gt"))
("one-of-three-dual-rail-dims-comp" ("dr_oot_dims_comp" 0 1 2 3 4 5 6) (1 "dr_oot_dims_comp"))
("one-of-three-dual-rail-ncl-comp" ("dr_oot_ncl_comp" 0 1 2 3 4 5 6) (1 "dr_oot_ncl_comp"))
("one-of-three-dims-comp" ("oot_dims_comp" 0 1 2 3 4 5 6 7 8) (1 "oot_dims_comp"))
("one-of-three-ncl-comp" ("oot_ncl_comp" 0 1 2 3 4 5 6 7 8) (1 "oot_ncl_comp"))
("dual-rail-latch" ("dr_latch" 0 1 2 3 4) (1 "dr_latch"))
("dual-rail-spacer-latch" ("dr_spacer_latch" 0 1 2 3 4) (1 "dr_spacer_latch"))
("dual-rail-ncl-latch" ("dr_ncl_latch" 0 1 2 3 4) (1 "dr_ncl_latch"))
("dual-rail-true-ncl-latch" ("dr_tncl_latch" 0 1 2 3 4 5) (1 "dr_tncl_latch"))
("one-of-four-latch" ("oof_latch" 0 1 2 3 4 5 6 7 8) (1 "oof_latch"))
("one-of-four-ncl-latch" ("oof_ncl_latch" 0 1 2 3 4 5 6 7 8) (1 "oof_ncl_latch"))
("one-of-four-true-ncl-reg" ("oof_tncl_latch" 0 1 2 3 4 5 6 7 8 9) (1 "oof_tncl_latch"))
balsa-tech-xilinx/xilinx/.svn/text-base/Makefile.am.svn-base0000444003172000014400000000052510212061546024206 0ustar tomswapt00000000000000## Process this file with automake to produce Makefile.in
techxilinxdir = $(datadir)/tech/xilinx
techxilinx_DATA = \
balsa-cells.net \
balsa-cells-caps.net \
components.abs \
gate-mappings \
gate-mappings-caps \
drive-table \
xilinx \
xilinx-cells.net \
xilinx-cells-caps.net \
balsa-mgr.cfg
EXTRA_DIST = \
$(techxilinx_DATA)
balsa-tech-xilinx/xilinx/.svn/text-base/components.abs.svn-base0000444003172000014400000002212010212061546025021 0ustar tomswapt00000000000000;;;
;;; `components.abs'
;;; Breeze primitive components for technology xilinx
;;;
;;; 10 Aug 2001, Andrew Bardsley
;;;
;;; $Id: components.abs,v 1.2 2004/06/02 14:06:11 taylors0 Exp $
;;;
(primitive-part "CallMux"
(parameters
("width" (named-type "cardinal"))
("inputCount" (named-type "cardinal"))
)
(ports
(arrayed-port "inp" passive input (numeric-type #f (param "width")) 0 (param "inputCount"))
(port "out" active output (numeric-type #f (param "width")))
)
(symbol
(centre-string "|")
)
(implementation
(style "four_b_rb"
(nodes
("muxOut" (param "width") 0 1)
("select" 1 0 1)
("nselect" 1 0 1)
("nwaySelect" (param "inputCount") 0 1)
("nwayMuxOut" (param "width") 0 (param "inputCount"))
)
(gates
(case (param "inputCount")
((2)
(cell "set-reset-flip-flop"
(req (bundle "inp" 1))
(req (bundle "inp" 0))
(node "select")
(node "nselect")
)
(and
(combine (ack (each "inp")))
(combine (node "nselect") (node "select"))
(combine (dup 2 (ack "out")))
)
(mux2 (req "out") (req (each "inp")) (node "select"))
(mux2 (data "out") (data (each "inp")) (combine (dup (param "width") (node "select"))))
)
(else
(or (req "out") (req (each "inp")))
(c-element
(combine (ack (each "inp")))
(combine (req (each "inp")))
(combine (dup (param "inputCount") (ack "out")))
)
(or
(node "nwaySelect")
(combine (ack (each "inp")))
(combine (req (each "inp")))
)
(nand
(combine (node (each "nwayMuxOut")))
(combine (data (each "inp")))
(combine (dup-each (param "width") (smash (node "nwaySelect"))))
)
(nand
(data "out")
(node (each "nwayMuxOut"))
)
)
)
)
)
(style "dual_b" (include tech "common" "data-dual/CallMux"))
(style "one_of_2_4" (include tech "common" "data-1of4/CallMux"))
)
)
(primitive-part "Variable"
(parameters
("width" (named-type "cardinal"))
("readPortCount" (named-type "cardinal"))
("name" (string) not-used)
)
(ports
(port "write" passive input (numeric-type #f (param "width")))
(arrayed-port "read" passive output (numeric-type #f (param "width")) 0 (param "readPortCount"))
)
(symbol
(centre-string (param "name"))
)
(implementation
(style "four_b_rb"
(nodes
("nWrite" 1 0 1)
)
(gates
(inv (node "nWrite") (req "write"))
(inv (ack "write") (node "nWrite"))
(latch (combine (dup (param "width") (node "nWrite"))) (data "write") (data (bundle "read" 0)))
)
(connections
(connect (combine (req (each "read"))) (combine (ack (each "read"))))
(if (>= (param "readPortCount") 2)
(connect (data (bundle "read" 0)) (data (bundles "read" 1 (- (param "readPortCount") 1))))
)
)
)
(style "dual_b"
(nodes
("qt" (param "width") 0 1)
("qf" (param "width") 0 1)
("wackt" (param "width") 0 1)
("wackf" (param "width") 0 1)
("wack" (param "width") 0 1)
("one" 1 0 1)
)
(gates
(vcc (node "one"))
; Flipflop: use a DFF with clear (xilinx FDC component)
(cell "edge-dff-clr"
(req1 "write") (combine (dup (param "width") (node "one")) )
(req0 "write") (node "qt")
)
; invert Q outputs
(inv (node "qf") (node "qt"))
; write ack signal generation
(nand (node "wackt") (req1 "write") (node "qt"))
(nand (node "wackf") (req0 "write") (node "qf"))
(nand (node "wack") (node "wackt") (node "wackf"))
(c-element (ack "write") (smash (node "wack")))
; Read ports
(and
(combine (ack1 (each "read")))
(combine (dup-each (param "width") (req (each "read"))))
(combine (dup (param "readPortCount") (node "qt")))
)
(and
(combine (ack0 (each "read")))
(combine (dup-each (param "width") (req (each "read"))))
(combine (dup (param "readPortCount") (node "qf")))
)
)
(connections
)
)
(style "one_of_2_4"
(defines
(width-odd (quotient (+ (param "width") 1) 2))
(width-even (quotient (param "width") 2))
(plural (> (param "width") 1)) ;; more than one
(odd (= (modulo (param "width") 2) 1))
)
(nodes
("store0" width-odd 0 1)
("store1" width-odd 0 1)
("store2" width-even 0 1)
("store3" width-even 0 1)
("orcomp" width-even 0 1)
("oddcomp" 1 0 1)
)
(gates
(if plural
(gates
(or (node "orcomp")
(slice 0 width-even (req0 "write"))(slice 0 width-even (req1 "write"))
(slice 0 width-even (req2 "write"))(slice 0 width-even (req3 "write")))
)
) ;; completion of input
(if odd
(gates
(or (node "oddcomp") (slice width-even 1 (req0 "write"))(slice width-even 1 (req1 "write")))
)
)
(if plural ;; producing ack to latch writes
(gates
(if odd
(c-element (ack "write") (smash (node "orcomp")) (node "oddcomp"))
(c-element (ack "write") (smash (node "orcomp")))
)
)
(connect (node "oddcomp") (ack "write"))
)
(if plural
(gates
(latch (combine (dup width-even (ack "write"))) (slice 0 width-even (req0 "write")) (slice 0 width-even (node "store0")))
(latch (combine (dup width-even (ack "write"))) (slice 0 width-even (req1 "write")) (slice 0 width-even (node "store1")))
(latch (combine (dup width-even (ack "write"))) (slice 0 width-even (req2 "write")) (slice 0 width-even (node "store2"))) ;; slicing maybe unnecessary
(latch (combine (dup width-even (ack "write"))) (slice 0 width-even (req3 "write")) (slice 0 width-even (node "store3")))
)
)
(if odd
(gates
(latch (ack "write") (slice width-even 1 (req0 "write")) (slice width-even 1 (node "store0")))
(latch (ack "write") (slice width-even 1 (req1 "write")) (slice width-even 1 (node "store1")))
)
)
; Read ports
(and (combine (ack0 (each "read"))) (combine (dup-each width-odd (req (each "read"))))
(combine (dup (param "readPortCount") (node "store0"))))
(and (combine (ack1 (each "read"))) (combine (dup-each width-odd (req (each "read"))))
(combine (dup (param "readPortCount") (node "store1"))))
(if plural
(gates
(and (combine (ack2 (each "read"))) (combine (dup-each width-even (req (each "read"))))
(combine (dup (param "readPortCount") (node "store2"))))
(and (combine (ack3 (each "read"))) (combine (dup-each width-even (req (each "read"))))
(combine (dup (param "readPortCount") (node "store3"))))
)
)
)
(connections)
)
)
)
(primitive-part "Arbiter" ; FIXME
(parameters
)
(ports
(sync-port "inpA" passive)
(sync-port "inpB" passive)
(sync-port "outA" active)
(sync-port "outB" active)
)
(symbol
(centre-string "(>")
)
(implementation
(style "four_b_rb"
(nodes
("miA" 1 0 1)
("miB" 1 0 1)
("moA" 1 0 1)
("moB" 1 0 1)
)
(gates
(mutex (node "miA") (node "miB") (node "moA") (node "moB"))
(or (node "miA") (req "inpA") (ack "outA"))
(or (node "miB") (req "inpB") (ack "outB"))
(and (req "outA") (node "moA") (req "inpA"))
(and (req "outB") (node "moB") (req "inpB"))
(connect (ack "outA") (ack "inpA"))
(connect (ack "outB") (ack "inpB"))
)
)
(style "dual_b" (include tech "common" "ctrl-broad/Arbiter"))
(style "one_of_2_4" (include tech "common" "ctrl-broad/Arbiter"))
)
)
(primitive-part "CaseFetch"
(parameters
("width" (named-type "cardinal"))
("indexWidth" (named-type "cardinal"))
("inputCount" (named-type "cardinal"))
("specification" (string))
)
(ports
(port "out" passive output (numeric-type #f (param "width")))
(port "index" active input (numeric-type #f (param "indexWidth")))
(arrayed-port "inp" active input (numeric-type #f (param "width")) 0 (param "inputCount"))
)
(symbol
(centre-string "@T" (param "specification"))
)
(implementation
(style "four_b_rb"
(nodes
("t" (param "indexWidth") 0 1)
("c" (param "indexWidth") 0 1)
("outputreq" 1 0 1)
("latchedIndex" (param "indexWidth") 0 1)
("muxOut" (param "width") 0 (param "inputCount"))
("elseAck" 1 0 1)
)
(gates
(s-element (req "out") (node "outputreq") (req "index") (ack "index"))
(latch (combine (dup (param "indexWidth") (req "index"))) (data "index") (node "latchedIndex"))
(demux2 (combine (dup (param "indexWidth") (node "outputreq"))) (node "c") (node "t") (node "latchedIndex"))
(if (complete-encoding? (param "specification") (param "indexWidth"))
(gates
(decode and-or (param "specification") (node "c") (node "t") (req (each "inp")))
(or (ack "out") (ack (each "inp")))
)
(gates
(decode and-or (param "specification") (node "c") (node "t") (req (each "inp")) (node "elseAck"))
(or (ack "out") (ack (each "inp")) (node "elseAck"))
)
)
(nand
(combine (node (each "muxOut")))
(combine (dup-each (param "width") (ack (each "inp"))))
(combine (data (each "inp")))
)
(nand
(data "out")
(node (each "muxOut"))
)
)
)
(style "dual_b" (include tech "common" "data-dual/CaseFetch"))
(style "one_of_2_4" (include tech "common" "data-1of4/CaseFetch"))
)
)
(include tech "common" ".." "components")
balsa-tech-xilinx/xilinx/.svn/text-base/balsa-mgr.cfg.svn-base0000444003172000014400000000407310212061546024502 0ustar tomswapt00000000000000(balsa-mgr-technology "xilinx"
(description "Generic Xilinx technology")
(balsa-netlist-options "-f -i helper")
(style-options
(style-option "sim"
(enumeration
("icarus" "Icarus Verilog")
("vxl" "Cadence Verilog-XL")
("ncv" "Cadence NC-Verilog")
("vcs" "Synonsys VCS")
("modelsim" "Modelsim")
("cver" "Cver")
)
"Simulator to use for implementation simulation"
)
(style-option "suggest-buffers"
(boolean)
"Add defaults buffers in suggested drive-up buffer insertion points"
)
(style-option "cad"
(enumeration
("ise" "Xilinx ISE tools")
("cadence" "Cadence Xilinx Design Flow")
)
"Target CAD tool"
)
)
(styles
(style "four_b_rb"
(description "Bundled data, single-rail, 4-phase broad/reduced-broad")
(allowed-style-options "sim" "suggest-buffers" "cad")
)
(style "dual_b"
(style-options
(style-option "logic"
(enumeration
("dims" "DIMS logic implementations")
("ncl" "NCL gates")
("balanced" (boolean) "`Balanced' logic")
)
"Style of dual-rail logic"
)
(style-option "variable"
(enumeration
("sr" "Set-rest flip-flops")
("spacer" "Reset-before-set variables")
("ncl" "NCL pipeline latch")
)
"Style of dual-rail variables"
)
(style-option "n-of-m-mapping" (boolean) "Unoptimised DIMS enc/decoders")
)
(description "Dual-rail with broad sync channels")
(allowed-style-options "sim" "suggest-buffers" "logic" "variable" "n-of-m-mapping" "cad")
)
(style "one_of_2_4"
(style-options
(style-option "logic"
(enumeration
("dims" "DIMS logic implementations")
("ncl" "NCL gates")
)
"Style of 1-of-4 logic"
)
(style-option "variable"
(enumeration
("sr" "Set-rest flip-flops")
("ncl" "NCL pipeline latch")
)
"Style of 1-of-4 variables"
)
(style-option "n-of-m-mapping" (boolean) "Unoptimised DIMS enc/decoders")
)
(description "1-of-4 with dual rail `odd' bits")
(allowed-style-options "sim" "suggest-buffers" "logic" "variable" "cad")
)
)
)
balsa-tech-xilinx/xilinx/.svn/text-base/gate-mappings-caps.svn-base0000444003172000014400000002757410212061546025572 0ustar tomswapt00000000000000;;;
;;; `gate-mappings-caps'
;;; Abstract->concrete gate mappings, for Xilinx 'Generic' technology
;;;
;;; 02 Jun 2004, Sam Taylor
;;; 02 Jul 1999, Andrew Bardsley
;;;
;;; This file has lists of (abs-gate-name default-real-gate . weighted-real-gates)
;;; The default real gate is used where nodal load management is not used and has the form:
;;; (gate-name . pin-mappings)
;;; The weighted-real-gates have the form:
;;; (output-drive gate-name . pin-mappings)
;;; The pin-mappings are lists of integers mapping abstract gate pin numbers to real gate pin
;;; numbers. The integers correspond to abstract gate pin positions (0 based) and their position
;;; to the position of that pin in the real gate. eg.
;;; (0 "q1and2d0" 2 1 0) is a drive 0 2-input and gate where pin 2 of the abstract gate (in2) is
;;; pin 0 of the real gate.
;;; and{n}: out,in1,in2...
("and2" ("AND2" 0 1 2) (1 "AND2"))
("and3" ("AND3" 0 1 2 3) (1 "AND3"))
("and4" ("AND4" 0 1 2 3 4) (1 "AND4"))
("and5" ("AND5" 0 1 2 3 4 5) (1 "AND5"))
;;; nand{n}: out,in1,in2...
("nand2" ("NAND2" 0 1 2) (1 "NAND2"))
("nand3" ("NAND3" 0 1 2 3) (1 "NAND3"))
("nand4" ("NAND4" 0 1 2 3 4) (1 "NAND4"))
("nand5" ("NAND5" 0 1 2 3 4 5) (1 "NAND5"))
;;; or{n}: out,in1,in2...
("or2" ("OR2" 0 1 2) (1 "OR2"))
("or3" ("OR3" 0 1 2 3) (1 "OR3"))
("or4" ("OR4" 0 1 2 3 4) (1 "OR4"))
("or5" ("OR5" 0 1 2 3 4 5) (1 "OR5"))
;;; nor{n}: out,in1,in2...
("nor2" ("NOR2" 0 1 2) (1 "NOR2"))
("nor3" ("NOR3" 0 1 2 3) (1 "NOR3"))
("nor4" ("NOR4" 0 1 2 3 4) (1 "NOR4"))
("nor5" ("NOR5" 0 1 2 3 4 5) (1 "NOR5"))
;;; xor2: out,in1,in2
("xor2" ("XOR2" 0 1 2) (1 "XOR2"))
;;; xnor2: out,in1,in2
("xnor2" ("XNOR2" 0 1 2) (1 "XNOR2"))
;;; inv: out,in
("inv" ("INV" 0 1) (1 "INV"))
;;; NB. buf is a driving buffer not a logical buffer
;;; buf: out,in
("buf" ("BUF" 0 1) (1 "BUF") (2 "BU2") (3 "BU3") (4 "BU4") (8 "BU8"))
("suggested-buffer" ("BUF" 0 1) (1 "BUF"))
;;; NB. connect is a logical buffer
;;; connect: out,in
("connect" ("BUF" 0 1) (1 "BUF"))
;;; latch: in,out,enable
("latch" ("FD" 2 0 1) (1 "FD"))
;;; Edge Triggered Flip Flop with async clear
("edge-dff-clr" ("FDC" 3 1 2 0) (1 "FDC"))
("adder" ("balsa_fa" 0 1 2 3 4 5 6 7) (1 "balsa_fa"))
;;; mutex: inA,inB,outA,outB
;;; mutual exclusion unit
("mutex" ("mutex1" 2 3 0 1) (1 "mutex1"))
;; helper cells
("and-or22" ("ao22" 0 1 2 3 4) (1 "ao22"))
("and-or-invert22" ("aoi22" 0 1 2 3 4) (1 "aoi22"))
("and-or222" ("ao222" 0 1 2 3 4 5 6) (1 "ao222"))
("and-or-invert222" ("aoi222" 0 1 2 3 4 5 6) (1 "aoi222"))
("set-reset-flip-flop" ("srff" 0 1 2 3) (1 "srff"))
("mux2" ("mux2" 0 1 2 3) (1 "mux2"))
("nmux2" ("nmux2" 0 1 2 3) (1 "nmux2"))
("single-rail-full-adder" ("balsa_fa" 0 1 2 3 4 5 6 7) (1 "balsa_fa"))
("c-element2" ("c2" 0 1 2) (1 "c2"))
("c-element3" ("c3" 0 1 2 3) (1 "c3"))
("inverted-c-element" ("nc2" 0 1 2) (1 "nc2"))
("inverted-assym-c-element" ("nc2p" 0 1 2) (1 "nc2p"))
("demux2" ("demux2" 0 1 2 3) (1 "demux2"))
("s-element" ("selem" 0 1 2 3) (1 "selem"))
("th22" ("th22" 0 1 2) (1 "th22"))
("th33" ("th33" 0 1 2 3) (1 "th33"))
("th23" ("th23" 0 1 2 3) (1 "th23"))
("th23w2" ("th23w2" 0 1 2 3) (1 "th23w2"))
("th24" ("th24" 0 1 2 3 4) (1 "th24"))
("th24w2" ("th24w2" 0 1 2 3 4) (1 "th24w2"))
("th24w22" ("th24w22" 0 1 2 3 4) (1 "th24w22"))
("th33w2" ("th33w2" 0 1 2 3) (1 "th33w2"))
("th34" ("th34" 0 1 2 3 4) (1 "th34"))
("th34w2" ("th34w2" 0 1 2 3 4) (1 "th34w2"))
("th34w22" ("th34w22" 0 1 2 3 4) (1 "th34w22"))
("dual-rail-and2" ("dr_and2" 0 1 2 3 4 5) (1 "dr_and2"))
("dual-rail-and2-bal" ("dr_and2_bal" 0 1 2 3 4 5) (1 "dr_and2_bal"))
("dual-rail-and2-ncl" ("dr_and2_ncl" 0 1 2 3 4 5) (1 "dr_and2_ncl"))
("dual-rail-or2" ("dr_or2" 0 1 2 3 4 5) (1 "dr_or2"))
("dual-rail-or2-bal" ("dr_or2_bal" 0 1 2 3 4 5) (1 "dr_or2_bal"))
("dual-rail-or2-ncl" ("dr_or2_ncl" 0 1 2 3 4 5) (1 "dr_or2_ncl"))
("dual-rail-nor2" ("dr_nor2" 0 1 2 3 4 5) (1 "dr_nor2"))
("dual-rail-nor2-ncl" ("dr_nor2_ncl" 0 1 2 3 4 5) (1 "dr_nor2_ncl"))
("dual-rail-xor2" ("dr_xor2" 0 1 2 3 4 5) (1 "dr_xor2"))
("dual-rail-xor2-ncl" ("dr_xor2_ncl" 0 1 2 3 4 5) (1 "dr_xor2_ncl"))
("dual-rail-ao21" ("dr_ao21" 0 1 2 3 4 5 6 7) (1 "dr_ao21"))
("dual-rail-ao21-bal" ("dr_ao21_bal" 0 1 2 3 4 5 6 7) (1 "dr_ao21_bal"))
("dual-rail-ao21-ncl" ("dr_ao21_ncl" 0 1 2 3 4 5 6 7) (1 "dr_ao21_ncl"))
("dual-rail-ineq-comp" ("dr_ineq_comp" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp"))
("dual-rail-ineq-comp-bal" ("dr_ineq_comp_bal" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp_bal"))
("dual-rail-ineq-comp-ncl" ("dr_ineq_comp_ncl" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp_ncl"))
("dual-rail-mux2" ("dr_mux2" 0 1 2 3 4 5 6 7) (1 "dr_mux2"))
("dual-rail-mux2-ncl" ("dr_mux2_ncl" 0 1 2 3 4 5 6 7) (1 "dr_mux2_ncl"))
("dual-rail-half-adder" ("dr_ha" 0 1 2 3 4 5 6 7) (1 "dr_ha"))
("dual-rail-half-adder-bal" ("dr_ha_bal" 0 1 2 3 4 5 6 7) (1 "dr_ha_bal"))
("dual-rail-half-adder-ncl" ("dr_ha_ncl" 0 1 2 3 4 5 6 7) (1 "dr_ha_ncl"))
("dual-rail-full-adder" ("dr_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_fa"))
("dual-rail-full-adder-bal" ("dr_fa_bal" 0 1 2 3 4 5 6 7 8 9) (1 "dr_fa_bal"))
("dual-rail-dims-adder" ("dr_dims_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_dims_fa"))
("dual-rail-ncl-adder" ("dr_ncl_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_ncl_fa"))
("dual-rail-full-adder-primed" ("dr_fa_p" 0 1 2 3 4 5 6 7) (1 "dr_fa_p"))
("dual-rail-full-adder-primed-bal" ("dr_fa_p_bal" 0 1 2 3 4 5 6 7) (1 "dr_fa_p_bal"))
("dual-rail-full-adder-primed-ncl" ("dr_fa_p_ncl" 0 1 2 3 4 5 6 7) (1 "dr_fa_p_ncl"))
("dual-rail-dims-subtracter" ("dr_dims_fs" 0 1 2 3 4 5 6 7 8 9) (1 "dr_dims_fs"))
("dual-rail-ncl-subtracter" ("dr_ncl_fs" 0 1 2 3 4 5 6 7 8 9) (1 "dr_ncl_fs"))
("one-of-four-half-adder" ("oof_ha" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ha"))
("one-of-four-dims-carry-adder" ("oof_dims_ca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_ca"))
("one-of-four-ncl-carry-adder" ("oof_ncl_ca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_ca"))
("oof_dims_ca_se" ("oof_dims_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dims_ca_se"))
("one-of-four-dims-carry-adder-overflow" ("oof_ncl_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ncl_ca_se"))
("one-of-four-full-adder" ("oof_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_fa"))
("one-of-four-dims-full-adder" ("oof_dims_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dims_fa"))
("one-of-four-dims-full-adder-overflow" ("oof_dims_fa_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17) (1 "oof_dims_fa_se"))
("one-of-four-dims-subtracter" ("oof_dims_fs" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dims_fs"))
("one-of-four-ncl-full-adder" ("oof_ncl_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_ncl_fa"))
("one-of-four-ncl-full-adder-overflow" ("oof_ncl_fa_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17) (1 "oof_ncl_fa_se"))
("one-of-four-ncl-subtracter" ("oof_ncl_fs" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_ncl_fs"))
("one-of-four-dims-primed-carry-adder" ("oof_dims_pca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_pca"))
("one-of-four-ncl-primed-carry-adder" ("oof_ncl_pca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_pca"))
("one-of-four-dims-primed-carry-adder-overflow" ("oof_dims_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dims_pca_se"))
("one-of-four-ncl-primed-carry-adder-overflow" ("oof_ncl_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ncl_pca_se"))
("one-of-four-dual-rail-dims-carry-adder" ("oof_dr_dims_ca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_dims_ca"))
("one-of-four-dual-rail-ncl-carry-adder" ("oof_dr_ncl_ca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_ncl_ca"))
("one-of-four-dual-rail-dims-carry-adder-overflow" ("oof_dr_dims_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_dims_ca_se"))
("one-of-four-dual-rail-ncl-carry-adder-overflow" ("oof_dr_ncl_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_ncl_ca_se"))
("one-of-four-dual-rail-dims-primed-carry-adder" ("oof_dr_dims_pca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_dims_pca"))
("one-of-four-dual-rail-ncl-primed-carry-adder" ("oof_dr_ncl_pca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_ncl_pca"))
("one-of-four-dual-rail-dims-primed-carry-adder-overflow" ("oof_dr_dims_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_dims_pca_se"))
("one-of-four-dual-rail--ncl-primed-carry-adder-overflow" ("oof_dr_ncl_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_ncl_pca_se"))
("one-of-four-dims-and2" ("oof_dims_and2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_and2"))
("one-of-four-ncl-and2" ("oof_ncl_and2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_and2"))
("one-of-four-dims-or2" ("oof_dims_or2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_or2"))
("one-of-four-ncl-or2" ("oof_ncl_or2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_or2"))
("one-of-four-dims-xor2" ("oof_dims_xor2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_xor2"))
("one-of-four-ncl-xor2" ("oof_ncl_xor2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_xor2"))
("oof_dims_equal" ("oof_dims_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_equal"))
("oof_ncl_equal" ("oof_ncl_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_equal"))
("oof_dr_dims_equal" ("oof_dr_dims_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dr_dims_equal"))
("oof_dr_ncl_equal" ("oof_dr_ncl_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dr_ncl_equal"))
("one-of-four-dims-inequal" ("oof_dims_inequal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_inequal"))
("one-of-four-ncl-inequal" ("oof_ncl_inequal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_inequal"))
("oof_dr_dims_inequal" ("oof_dr_dims_inequal" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_inequal"))
("one-of-four-dual-rail-ncl-inequal" ("oof_dr_ncl_inequal" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_inequal"))
("one-of-four-dims-comp" ("oof_dims_comp" 0 1 2 3 4 5 6 7 8 9 10) (1 "oof_dims_comp"))
("one-of-four-ncl-comp" ("oof_ncl_comp" 0 1 2 3 4 5 6 7 8 9 10) (1 "oof_ncl_comp"))
("oof_dr_dims_ineq_comp" ("oof_dr_dims_ineq_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_dims_ineq_comp"))
("oof_dr_ncl_ineq_comp" ("oof_dr_ncl_ineq_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_ncl_ineq_comp"))
("oof_dr_dims_ineq_sgn_comp" ("oof_dr_dims_ineq_sgn_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_dims_ineq_sgn_comp"))
("oof_dr_ncl_ineq_sgn_comp" ("oof_dr_ncl_ineq_sgn_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_ncl_ineq_sgn_comp"))
("one-of-four-dims-less-than" ("oof_dims_lt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_lt"))
("one-of-four-ncl-less-than" ("oof_ncl_lt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_lt"))
("one-of-four-dims-greater-than" ("oof_dims_gt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_gt"))
("one-of-four-ncl-greater-than" ("oof_ncl_gt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_gt"))
("one-of-four-dual-rail-dims-less-than" ("oof_dr_dims_lt" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_lt"))
("one-of-four-dual-rail-ncl-less-than" ("oof_dr_ncl_lt" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_lt"))
("one-of-four-dual-rail-dims-greater-than" ("oof_dr_dims_gt" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_gt"))
("one-of-four-dual-rail-ncl-greater-than" ("oof_dr_ncl_gt" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_gt"))
("dual-rail-dims-comp" ("dr_dims_comp" 0 1 2 3 4 5 6) (1 "dr_dims_comp"))
("dual-rail-ncl-comp" ("dr_ncl_comp" 0 1 2 3 4 5 6) (1 "dr_ncl_comp"))
("dual-rail-dims-less-than" ("dr_dims_lt" 0 1 2 3 4 5) (1 "dr_dims_lt"))
("dual-rail-ncl-less-than" ("dr_ncl_lt" 0 1 2 3 4 5) (1 "dr_ncl_lt"))
("dual-rail-dims-greater-than" ("dr_dims_gt" 0 1 2 3 4 5) (1 "dr_dims_gt"))
("dual-rail-ncl-greater-than" ("dr_ncl_gt" 0 1 2 3 4 5) (1 "dr_ncl_gt"))
("one-of-three-dual-rail-dims-comp" ("dr_oot_dims_comp" 0 1 2 3 4 5 6) (1 "dr_oot_dims_comp"))
("one-of-three-dual-rail-ncl-comp" ("dr_oot_ncl_comp" 0 1 2 3 4 5 6) (1 "dr_oot_ncl_comp"))
("one-of-three-dims-comp" ("oot_dims_comp" 0 1 2 3 4 5 6 7 8) (1 "oot_dims_comp"))
("one-of-three-ncl-comp" ("oot_ncl_comp" 0 1 2 3 4 5 6 7 8) (1 "oot_ncl_comp"))
("dual-rail-latch" ("dr_latch" 0 1 2 3 4) (1 "dr_latch"))
("dual-rail-spacer-latch" ("dr_spacer_latch" 0 1 2 3 4) (1 "dr_spacer_latch"))
("dual-rail-ncl-latch" ("dr_ncl_latch" 0 1 2 3 4) (1 "dr_ncl_latch"))
("dual-rail-true-ncl-latch" ("dr_tncl_latch" 0 1 2 3 4 5) (1 "dr_tncl_latch"))
("one-of-four-latch" ("oof_latch" 0 1 2 3 4 5 6 7 8) (1 "oof_latch"))
("one-of-four-ncl-latch" ("oof_ncl_latch" 0 1 2 3 4 5 6 7 8) (1 "oof_ncl_latch"))
("one-of-four-true-ncl-reg" ("oof_tncl_latch" 0 1 2 3 4 5 6 7 8 9) (1 "oof_tncl_latch"))
balsa-tech-xilinx/xilinx/.svn/text-base/xilinx.svn-base0000444003172000014400000000225210212061546023407 0ustar tomswapt00000000000000;;;
;;; `xilinx'
;;; Generic Xilinx tech. description
;;;
;;; 2004-06-02, Sam Taylor
;;; 2002-10-15, Andrew Bardsley
;;;
(define purpose (let ((purpose (assoc "cad" breeze-style-options)))
(if purpose (cdr purpose) "cadence")))
(net-signature-for-netlist-format 'verilog #t)
;;; max. no. of inputs for and/or/nand/nor gates and c-elements
(set! tech-gate-max-fan-in 4)
(set! tech-c-element-max-fan-in 3)
(set! tech-map-cell-name (net-simple-cell-name-mapping #f)) ;;; mapping
(set! tech-cell-name-max-length 64)
(if (string=? purpose "cadence")
(begin
(set! tech-gnd-component-name "gnd")
(set! tech-vcc-component-name "vcc")
(set! breeze-gates-net-files '("xilinx-cells" "balsa-cells"))
(set! breeze-gates-mapping-file (string-append breeze-tech-dir "gate-mappings")))
(begin
(set! tech-gnd-component-name "GND")
(set! tech-vcc-component-name "VCC")
(set! breeze-gates-net-files '("xilinx-cells-caps" "balsa-cells-caps"))
(set! breeze-gates-mapping-file (string-append breeze-tech-dir "gate-mappings-caps")))
)
(set! breeze-primitives-file (string-append breeze-tech-dir "components.abs"))
(set! breeze-gates-drive-file (string-append breeze-tech-dir "drive-table"))
balsa-tech-xilinx/xilinx/.svn/text-base/xilinx-cells.net.svn-base0000444003172000014400000003420710212061546025301 0ustar tomswapt00000000000000;;;
;;; `xilinx-cells.net'
;;; Xilinx Common Cells
;;;
;;; 02 Jun 2004, Sam Taylor
;;; 21 Jul 1999, Andrew Bardsley
;;;
(circuit "and2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "and2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "and2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "and3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "and3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "and3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "and3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "and4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nand2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nand2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nand3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nand3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nand3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nand3b3" (ports
("o" output 1)("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nand4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "or2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "or2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "or3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "or3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "or3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "or3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "or4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor1" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "nor2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nor2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nor2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nor3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nor3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nor3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nor3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nor4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xor2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xor2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xor3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xor3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xor3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xor3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xor4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xnor2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xnor2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xnor3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xnor3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xnor3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xnor3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xnor4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "gnd" (ports
("g" output 1)) (nets) (instances))
(circuit "vcc" (ports
("p" output 1)) (nets) (instances))
(circuit "inv" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "buff" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "fd" (ports ("q" output 1) ("c" input 1) ("d" input 1)) (nets) (instances))
(circuit "fdc" (ports ("q" output 1) ("c" input 1) ("clr" input 1)
("d" input 1)) (nets) (instances))
(circuit "fdce" (ports ("q" output 1) ("c" input 1) ("ce" input 1) ("clr" input 1)
("d" input 1)) (nets) (instances))
balsa-tech-xilinx/xilinx/.svn/text-base/xilinx-cells-caps.net.svn-base0000444003172000014400000003421310212061546026222 0ustar tomswapt00000000000000;;;
;;; `xilinx-cells-caps.net'
;;; Xilinx Common Cells
;;;
;;; 02 Jun 2004, Sam Taylor
;;; 21 Jul 1999, Andrew Bardsley
;;;
(circuit "AND2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "AND2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "AND2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "AND3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "AND3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "AND3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "AND3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "AND4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NAND2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NAND2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NAND3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NAND3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NAND3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NAND3B3" (ports
("o" output 1)("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NAND4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "OR2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "OR2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "OR3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "OR3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "OR3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "OR3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "OR4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR1" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "NOR2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NOR2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NOR2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NOR3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NOR3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NOR3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NOR3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NOR4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XOR2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XOR2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XOR3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XOR3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XOR3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XOR3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XOR4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XNOR2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XNOR2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XNOR3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XNOR3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XNOR3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XNOR3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XNOR4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "GND" (ports
("g" output 1)) (nets) (instances))
(circuit "VCC" (ports
("p" output 1)) (nets) (instances))
(circuit "INV" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "BUF" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "FD" (ports ("q" output 1) ("c" input 1) ("d" input 1)) (nets) (instances))
(circuit "FDC" (ports ("q" output 1) ("c" input 1) ("clr" input 1)
("d" input 1)) (nets) (instances))
(circuit "FDCE" (ports ("q" output 1) ("c" input 1) ("ce" input 1) ("clr" input 1)
("d" input 1)) (nets) (instances))
balsa-tech-xilinx/xilinx/.svn/text-base/balsa-cells.net.svn-base0000444003172000014400000042541110212061546025051 0ustar tomswapt00000000000000;;; `helper-cells'
;;; xilinx Balsa helper cells
;;; Created: Mon Mar 8 15:50:44 GMT 2004
;;; By: Sam Taylor (Linux)
;;; With net-net version: 20031009
(circuit "mutex1"
(ports
("q0" output 1)
("q1" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "nor2" (("int_0n" 0) "i0" ("int_0n" 1)))
(instance "nor2" (("int_0n" 1) "i1" ("int_0n" 1)))
(instance "nor3" ("q0" ("int_0n" 0) ("int_0n" 0) ("int_0n" 0)))
(instance "nor3" ("q1" ("int_0n" 1) ("int_0n" 1) ("int_0n" 1)))
)
(attributes (cell-type "helper"))
)
(circuit "ao22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "or2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "and2" (("int_0n" 1) "i2" "i3"))
(instance "and2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "aoi22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "nor2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "and2" (("int_0n" 1) "i2" "i3"))
(instance "and2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "ao222"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
("i4" input 1)
("i5" input 1)
)
(nets
("int_0n" 3)
)
(instances
(instance "or3" ("q" ("int_0n" 0) ("int_0n" 1) ("int_0n" 2)))
(instance "and2" (("int_0n" 2) "i4" "i5"))
(instance "and2" (("int_0n" 1) "i2" "i3"))
(instance "and2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "aoi222"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
("i4" input 1)
("i5" input 1)
)
(nets
("int_0n" 3)
)
(instances
(instance "nor3" ("q" ("int_0n" 0) ("int_0n" 1) ("int_0n" 2)))
(instance "and2" (("int_0n" 2) "i4" "i5"))
(instance "and2" (("int_0n" 1) "i2" "i3"))
(instance "and2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "srff"
(ports
("s" input 1)
("r" input 1)
("q" output 1)
("nq" output 1)
)
(nets
)
(instances
(instance "nor2" ("nq" "q" "s"))
(instance "nor2" ("q" "nq" "r"))
)
(attributes (simulation-initialise ("q" 0)) (cell-type "helper"))
)
(circuit "mux2"
(ports
("q" output 1)
("d0" input 1)
("d1" input 1)
("sel" input 1)
)
(nets
("int_0n" 2)
("nsel_0n" 1)
)
(instances
(instance "nand2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "nand2" (("int_0n" 1) "d1" "sel"))
(instance "nand2" (("int_0n" 0) "d0" ("nsel_0n" 0)))
(instance "inv" (("nsel_0n" 0) "sel"))
)
(attributes (cell-type "helper"))
)
(circuit "nmux2"
(ports
("q" output 1)
("d0" input 1)
("d1" input 1)
("sel" input 1)
)
(nets
("int_0n" 2)
("nsel_0n" 1)
("nq_0n" 1)
)
(instances
(instance "inv" ("q" ("nq_0n" 0)))
(instance "nand2" (("nq_0n" 0) ("int_0n" 0) ("int_0n" 1)))
(instance "nand2" (("int_0n" 1) "d1" "sel"))
(instance "nand2" (("int_0n" 0) "d0" ("nsel_0n" 0)))
(instance "inv" (("nsel_0n" 0) "sel"))
)
(attributes (cell-type "helper"))
)
(circuit "balsa_fa"
(ports
("nStart" input 1)
("A" input 1)
("B" input 1)
("nCVi" input 1)
("Ci" input 1)
("nCVo" output 1)
("Co" output 1)
("sum" output 1)
)
(nets
("start_0n" 1)
("ha_0n" 1)
("cv_0n" 1)
)
(instances
(instance "xor2" ("sum" ("ha_0n" 0) "Ci"))
(instance "xor2" (("ha_0n" 0) "A" "B"))
(instance "mux2" ("Co" "A" "Ci" ("ha_0n" 0)))
(instance "nmux2" ("nCVo" ("start_0n" 0) ("cv_0n" 0) ("ha_0n" 0)))
(instance "nor2" (("cv_0n" 0) "nStart" "nCVi"))
(instance "inv" (("start_0n" 0) "nStart"))
)
(attributes (cell-type "helper"))
)
(circuit "c2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
)
(instances
(instance "ao222" ("q" "i0" "i1" "i0" "q" "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "c3"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("qint_0n" 1)
)
(instances
(instance "c2" ("q" "i2" ("qint_0n" 0)))
(instance "c2" (("qint_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "nc2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("nq_0n" 1)
)
(instances
(instance "aoi222" ("q" "i0" "i1" "i0" ("nq_0n" 0) "i1" ("nq_0n" 0)))
(instance "inv" (("nq_0n" 0) "q"))
)
(attributes (cell-type "helper"))
)
(circuit "nc2p"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("nq_0n" 1)
)
(instances
(instance "aoi22" ("q" "i0" "i1" "i0" ("nq_0n" 0)))
(instance "inv" (("nq_0n" 0) "q"))
)
(attributes (cell-type "helper"))
)
(circuit "demux2"
(ports
("i" input 1)
("o0" output 1)
("o1" output 1)
("s" input 1)
)
(nets
("ns_0n" 1)
)
(instances
(instance "and2" ("o1" "i" "s"))
(instance "and2" ("o0" "i" ("ns_0n" 0)))
(instance "inv" (("ns_0n" 0) "s"))
)
(attributes (cell-type "helper"))
)
(circuit "selem"
(ports
("Ar" input 1)
("Aa" output 1)
("Br" output 1)
("Ba" input 1)
)
(nets
("s_0n" 1)
)
(instances
(instance "nc2p" (("s_0n" 0) "Ar" "Ba"))
(instance "nor2" ("Aa" "Ba" ("s_0n" 0)))
(instance "and2" ("Br" "Ar" ("s_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "th22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("qint_0n" 3)
)
(instances
(instance "or3" ("q" ("qint_0n" 0) ("qint_0n" 1) ("qint_0n" 2)))
(instance "and2" (("qint_0n" 2) "i1" "q"))
(instance "and2" (("qint_0n" 1) "i0" "q"))
(instance "and2" (("qint_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "th33"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("qint_0n" 2)
)
(instances
(instance "or2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "or3" (("qint_0n" 1) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "and2" (("qint_0n" 0) "i1" "i2"))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th23"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 2)
("qint_0n" 2)
("sinti_0n" 1)
)
(instances
(instance "or2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "or2" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1)))
(instance "and2" (("sint_0n" 1) "i0" ("sinti_0n" 0)))
(instance "and2" (("sint_0n" 0) "i1" "i2"))
(instance "or2" (("sinti_0n" 0) "i1" "i2"))
(instance "or3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th23w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 2)
("sint_0n" 1)
)
(instances
(instance "or4" ("q" "i0" ("hint_0n" 0) ("hint_0n" 1) ("sint_0n" 0)))
(instance "and2" (("sint_0n" 0) "i1" "i2"))
(instance "and2" (("hint_0n" 1) "i2" "q"))
(instance "and2" (("hint_0n" 0) "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 4)
("sint_0n" 6)
("qint_0n" 3)
)
(instances
(instance "or3" ("q" ("qint_0n" 0) ("qint_0n" 1) ("qint_0n" 2)))
(instance "or3" (("qint_0n" 2) ("sint_0n" 3) ("sint_0n" 4) ("sint_0n" 5)))
(instance "or3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "and2" (("sint_0n" 5) "i2" "i3"))
(instance "and2" (("sint_0n" 4) "i1" "i3"))
(instance "and2" (("sint_0n" 3) "i1" "i2"))
(instance "and2" (("sint_0n" 2) "i0" "i3"))
(instance "and2" (("sint_0n" 1) "i0" "i2"))
(instance "and2" (("sint_0n" 0) "i0" "i1"))
(instance "or4" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2) ("hint_0n" 3)))
(instance "and2" (("hint_0n" 3) "i3" "q"))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 3)
("qint_0n" 2)
)
(instances
(instance "or3" ("q" ("qint_0n" 0) ("qint_0n" 1) "i0"))
(instance "or3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "and2" (("sint_0n" 2) "i2" "i3"))
(instance "and2" (("sint_0n" 1) "i1" "i3"))
(instance "and2" (("sint_0n" 0) "i1" "i2"))
(instance "or3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "and2" (("hint_0n" 2) "i3" "q"))
(instance "and2" (("hint_0n" 1) "i2" "q"))
(instance "and2" (("hint_0n" 0) "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24w22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 2)
("sint_0n" 1)
("qint_0n" 1)
)
(instances
(instance "or3" ("q" "i0" "i1" ("qint_0n" 0)))
(instance "or3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("sint_0n" 0)))
(instance "and2" (("sint_0n" 0) "i2" "i3"))
(instance "and2" (("hint_0n" 1) "i3" "q"))
(instance "and2" (("hint_0n" 0) "i2" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th33w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 1)
("qint_0n" 2)
)
(instances
(instance "or2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "or3" (("qint_0n" 2) ("sint_0n" 3) ("sint_0n" 4) ("sint_0n" 5)))
(instance "or3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "and2" (("qint_0n" 1) "i0" ("sint_0n" 0)))
(instance "or2" (("sint_0n" 0) "i1" "i2"))
(instance "or3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th34"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 4)
("sint_0n" 2)
("qint_0n" 2)
("sinti_0n" 2)
)
(instances
(instance "or2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "or2" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1)))
(instance "and3" (("sint_0n" 1) "i1" "i3" ("sinti_0n" 1)))
(instance "or2" (("sinti_0n" 1) "i0" "i2"))
(instance "and3" (("sint_0n" 0) "i0" "i2" ("sinti_0n" 0)))
(instance "or2" (("sinti_0n" 0) "i1" "i3"))
(instance "or4" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2) ("hint_0n" 3)))
(instance "and2" (("hint_0n" 3) "i3" "q"))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th34w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q" ("mint_0n" 0) ("mint_0n" 1) "i0"))
(instance "or3" (("mint_0n" 1) "i1" "i2" "i3"))
(instance "c3" (("mint_0n" 0) "i1" "i2" "i3"))
)
(attributes (cell-type "helper"))
)
(circuit "th34w22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "th23" ("q" ("mint_0n" 0) "i0" "i1"))
(instance "or2" (("mint_0n" 0) "i2" "i3"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "or3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
(instance "c2" ("q_1" "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
(instance "or3" ("q_1" "gnd" ("n3_0n" 0) "gnd"))
(instance "c2" (("n3_0n" 0) "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "c2" ("q_1" "i0_1" "i1_1"))
(instance "th34w22" ("q_0" "i0_0" "i1_0" "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "c2" ("q_0" "i0_0" "i1_0"))
(instance "or3" ("q_1" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("q_0" "gnd" ("n3_0n" 0) "gnd"))
(instance "c2" (("n3_0n" 0) "i0_0" "i1_0"))
(instance "or3" ("q_1" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "th34w22" ("q_1" "i0_1" "i1_1" "i0_0" "i1_0"))
(instance "c2" ("q_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_nor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "c2" ("q_1" "i0_0" "i1_0"))
(instance "or3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_nor2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "c2" ("q_1" "i0_0" "i1_0"))
(instance "th34w22" ("q_0" "i0_1" "i1_1" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or2" ("q_0" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "or2" ("q_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_xor2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "th23w2" ("q_1" ("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "th23w2" ("q_0" ("n0_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2_bal" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2_bal" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2_ncl" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2_ncl" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21_bal" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2_bal" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21_ncl" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2_ncl" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_mux2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("s_0" input 1)
("s_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or2" ("q_0" ("n0_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "s_0" "i0_0"))
(instance "c2" (("n2_0n" 0) "s_1" "i1_0"))
(instance "or2" ("q_1" ("n1_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n1_0n" 0) "s_0" "i0_1"))
(instance "c2" (("n3_0n" 0) "s_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_mux2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("s_0" input 1)
("s_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "th23w2" ("q_1" ("n1_0n" 0) "s_0" "i0_1"))
(instance "c2" (("n1_0n" 0) "s_1" "i1_1"))
(instance "th23w2" ("q_0" ("n0_0n" 0) "s_0" "i0_0"))
(instance "c2" (("n0_0n" 0) "s_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "or3" ("co_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_0" ("n0_0n" 0) "co_1"))
(instance "c2" ("co_1" "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("co_1" "gnd" ("n3_0n" 0) "gnd"))
(instance "or3" ("co_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_0" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha_ncl"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
)
(instances
(instance "th23w2" ("co_0" "sum_1" "a_0" "b_0"))
(instance "th23w2" ("sum_1" ("n0_0n" 0) "a_1" "b_0"))
(instance "c2" (("n0_0n" 0) "a_0" "b_1"))
(instance "th23w2" ("sum_0" "co_1" "a_0" "b_0"))
(instance "c2" ("co_1" "a_1" "b_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("ha__1_0n" 1)
("ha__0_0n" 1)
("n0__1_0n" 1)
("n0_0n" 1)
)
(instances
(instance "th23w2" ("co_0" "sum_1" "a_0" "b_0"))
(instance "th23w2" ("sum_1" ("n0_0n" 0) "a_1" "b_0"))
(instance "c2" (("n0_0n" 0) "a_0" "b_1"))
(instance "th23w2" ("sum_0" "co_1" "a_0" "b_0"))
(instance "c2" ("co_1" "a_1" "b_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("ha__1_0n" 1)
("ha__0_0n" 1)
("n0__1_0n" 1)
("n0__0_0n" 1)
("n1__1_0n" 1)
("n1__0_0n" 1)
)
(instances
(instance "dr_xor2" (("n0__0_0n" 0) ("n0__1_0n" 0) ("n1__0_0n" 0) ("n1__1_0n" 0) "co_0" "co_1"))
(instance "dr_ha_bal" (("ha__0_0n" 0) ("ha__1_0n" 0) "ci_0" "ci_1" ("n1__0_0n" 0) ("n1__1_0n" 0) "sum_0" "sum_1"))
(instance "dr_ha_bal" ("a_0" "a_1" "b_0" "b_1" ("n0__0_0n" 0) ("n0__1_0n" 0) ("ha__0_0n" 0) ("ha__1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_fa"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("minterm_0n" 8)
)
(instances
(instance "or4" ("co0" ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4)))
(instance "or4" ("co1" ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 7)))
(instance "or4" ("sum0" ("minterm_0n" 0) ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "or4" ("sum1" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4) ("minterm_0n" 7)))
(instance "c3" (("minterm_0n" 7) "a1" "b1" "ci1"))
(instance "c3" (("minterm_0n" 6) "a1" "b1" "ci0"))
(instance "c3" (("minterm_0n" 5) "a1" "b0" "ci1"))
(instance "c3" (("minterm_0n" 4) "a1" "b0" "ci0"))
(instance "c3" (("minterm_0n" 3) "a0" "b1" "ci1"))
(instance "c3" (("minterm_0n" 2) "a0" "b1" "ci0"))
(instance "c3" (("minterm_0n" 1) "a0" "b0" "ci1"))
(instance "c3" (("minterm_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_fa"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
)
(instances
(instance "th34w2" ("sum1" "co0" "a1" "b1" "ci1"))
(instance "th34w2" ("sum0" "co1" "a0" "b0" "ci0"))
(instance "th23" ("co1" "a1" "b1" "ci1"))
(instance "th23" ("co0" "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("co_1" ("n1_0n" 0) ("n2_0n" 0) ("n3_0n" 0)))
(instance "or2" ("sum_0" ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_1" "co_0" ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" ("co_0" "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("co_0" "gnd" ("n0_0n" 0) "gnd"))
(instance "or3" ("co_1" ("n1_0n" 0) ("n2_0n" 0) ("n3_0n" 0)))
(instance "or2" ("sum_0" ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_1" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p_ncl"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "th23w2" ("co_1" "sum_0" "a_0" "b_1"))
(instance "th23w2" ("sum_1" "co_0" "a_1" "b_1"))
(instance "c2" ("co_0" "a_0" "b_0"))
(instance "th23w2" ("sum_0" ("n0_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_1" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_fs"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("minterm_0n" 8)
)
(instances
(instance "or4" ("co1" ("minterm_0n" 0) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "or4" ("co0" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3) ("minterm_0n" 7)))
(instance "or4" ("sum1" ("minterm_0n" 0) ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "or4" ("sum0" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4) ("minterm_0n" 7)))
(instance "c3" (("minterm_0n" 7) "a1" "b1" "ci1"))
(instance "c3" (("minterm_0n" 6) "a1" "b1" "ci0"))
(instance "c3" (("minterm_0n" 5) "a1" "b0" "ci1"))
(instance "c3" (("minterm_0n" 4) "a1" "b0" "ci0"))
(instance "c3" (("minterm_0n" 3) "a0" "b1" "ci1"))
(instance "c3" (("minterm_0n" 2) "a0" "b1" "ci0"))
(instance "c3" (("minterm_0n" 1) "a0" "b0" "ci1"))
(instance "c3" (("minterm_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_fs"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("cint_0n" 2)
)
(instances
(instance "th23" ("co1" ("cint_0n" 0) "b1" ("ci1_0n" 0)))
(instance "th23" ("co0" ("cint_0n" 1) "b0" ("ci0_0n" 0)))
(instance "th34w2" ("sum1" ("cint_0n" 0) "a1" "b1" "ci1"))
(instance "th34w2" ("sum0" ("cint_0n" 1) "a0" "b0" "ci0"))
(instance "th23" (("cint_0n" 1) "a1" "b1" "ci1"))
(instance "th23" (("cint_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ha"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 4)
)
(instances
(instance "or3" ("co_1" ("sopint_0n" 0) ("sopint_0n" 2) ("mint_0n" 11)))
(instance "or4" ("co_0" ("mint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 3) "sum_3"))
(instance "or4" ("sum_3" ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or2" ("sum_2" ("sopint_0n" 3) ("mint_0n" 11)))
(instance "or2" ("sum_1" ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "or2" ("sum_0" ("mint_0n" 0) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 3) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 10)))
(instance "or2" (("sopint_0n" 2) ("mint_0n" 6) ("mint_0n" 7)))
(instance "or2" (("sopint_0n" 1) ("mint_0n" 4) ("mint_0n" 5)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 14) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 13) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 12) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 11) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 9) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 6) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "or2" ("sum_3" ("mint_0n" 5) ("mint_0n" 6)))
(instance "or2" ("sum_2" ("mint_0n" 3) ("mint_0n" 4)))
(instance "or2" ("sum_1" ("mint_0n" 1) ("mint_0n" 2)))
(instance "or2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 4)
)
(instances
(instance "or4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "th23w2" ("sum_3" ("mint_0n" 3) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_1"))
(instance "th23w2" ("sum_2" ("mint_0n" 2) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "or2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or2" ("s_1" ("mint_0n" 4) "sum_3"))
(instance "or4" ("s_0" ("mint_0n" 0) "sum_1" ("mint_0n" 3) "co_1"))
(instance "or4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "or2" ("sum_3" ("mint_0n" 5) ("mint_0n" 6)))
(instance "or2" ("sum_2" ("mint_0n" 3) ("mint_0n" 4)))
(instance "or2" ("sum_1" ("mint_0n" 1) ("mint_0n" 2)))
(instance "or2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or2" ("s_1" ("mint_0n" 3) "sum_3"))
(instance "or4" ("s_0" ("mint_0n" 0) "sum_1" ("mint_0n" 2) "co_1"))
(instance "or4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "th23w2" ("sum_3" ("mint_0n" 4) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "or2" ("sum_2" ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "or2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("halfsum_0n" 4)
("halfcar_0n" 4)
)
(instances
(instance "dr_xor2" (("halfcar_0n" 0) ("halfcar_0n" 1) ("halfcar_0n" 2) ("halfcar_0n" 3) "co_0" "co_1"))
(instance "oof_dims_ca" (("halfsum_0n" 0) ("halfsum_0n" 1) ("halfsum_0n" 2) ("halfsum_0n" 3) "ci_0" "ci_1" ("halfcar_0n" 2) ("halfcar_0n" 3) "sum_0" "sum_1" "sum_2" "sum_3"))
(instance "oof_ha" ("i0_0" "i0_1" "i0_2" "i0_3" "i1_0" "i1_1" "i1_2" "i1_3" ("halfcar_0n" 0) ("halfcar_0n" 1) ("halfsum_0n" 0) ("halfsum_0n" 1) ("halfsum_0n" 2) ("halfsum_0n" 3)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
)
(instances
(instance "or4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "or4" (("carrint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "or4" (("carrint_0n" 6) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "or4" (("carrint_0n" 5) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 21) ("minterm_0n" 22)))
(instance "or4" (("carrint_0n" 4) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "or4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "or4" (("carrint_0n" 3) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24)))
(instance "or4" (("carrint_0n" 2) ("minterm_0n" 9) ("minterm_0n" 10) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or4" (("carrint_0n" 1) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8)))
(instance "or4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "or2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "or4" (("sumint_0n" 7) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "or4" (("sumint_0n" 6) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "or4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "or4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "or2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "or4" (("sumint_0n" 3) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "or4" (("sumint_0n" 2) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "or2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "or4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "or4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fa_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
("overint_0n" 8)
)
(instances
(instance "or4" ("s_1" ("overint_0n" 4) ("overint_0n" 5) ("overint_0n" 6) ("overint_0n" 7)))
(instance "or4" (("overint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "or4" (("overint_0n" 6) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 23) ("minterm_0n" 24)))
(instance "or4" (("overint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 20)))
(instance "or4" (("overint_0n" 4) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 12)))
(instance "or4" ("s_0" ("overint_0n" 0) ("overint_0n" 1) ("overint_0n" 2) ("overint_0n" 3)))
(instance "or4" (("overint_0n" 3) ("minterm_0n" 19) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "or4" (("overint_0n" 2) ("minterm_0n" 11) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "or4" (("overint_0n" 1) ("minterm_0n" 7) ("minterm_0n" 8) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "or4" (("overint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "or4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "or4" (("carrint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "or4" (("carrint_0n" 6) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "or4" (("carrint_0n" 5) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 21) ("minterm_0n" 22)))
(instance "or4" (("carrint_0n" 4) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "or4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "or4" (("carrint_0n" 3) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24)))
(instance "or4" (("carrint_0n" 2) ("minterm_0n" 9) ("minterm_0n" 10) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or4" (("carrint_0n" 1) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8)))
(instance "or4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "or2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "or4" (("sumint_0n" 7) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "or4" (("sumint_0n" 6) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "or4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "or4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "or2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "or4" (("sumint_0n" 3) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "or4" (("sumint_0n" 2) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "or2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "or4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "or4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fs"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
)
(instances
(instance "or4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "or4" (("carrint_0n" 7) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 23) ("minterm_0n" 31)))
(instance "or4" (("carrint_0n" 6) ("minterm_0n" 12) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "or4" (("carrint_0n" 5) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 7) ("minterm_0n" 11)))
(instance "or4" (("carrint_0n" 4) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3) ("minterm_0n" 4)))
(instance "or4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "or4" (("carrint_0n" 3) ("minterm_0n" 27) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "or4" (("carrint_0n" 2) ("minterm_0n" 20) ("minterm_0n" 24) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "or4" (("carrint_0n" 1) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 19)))
(instance "or4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 8) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "or2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "or4" (("sumint_0n" 7) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "or4" (("sumint_0n" 6) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "or4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "or4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "or2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "or4" (("sumint_0n" 3) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "or4" (("sumint_0n" 2) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "or2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "or4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "or4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 6)
("assoc_0n" 6)
("eqv_0n" 4)
("fsum_0n" 4)
("fcar_0n" 2)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 0)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 1)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 0)))
(instance "or4" (("fcar_0n" 1) ("assoc_0n" 4) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "or4" (("fcar_0n" 0) ("assoc_0n" 0) ("assoc_0n" 1) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "or3" (("fsum_0n" 3) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 2)))
(instance "or3" (("fsum_0n" 2) ("assoc_0n" 1) ("eqv_0n" 1) ("eqv_0n" 3)))
(instance "or2" (("fsum_0n" 1) ("assoc_0n" 0) ("assoc_0n" 5)))
(instance "or2" (("fsum_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "c2" (("eqv_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("eqv_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("eqv_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("eqv_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" (("assoc_0n" 5) ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23w2" (("assoc_0n" 4) ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23w2" (("assoc_0n" 3) ("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("assoc_0n" 2) ("mint_0n" 2) "i0_3" "i1_0"))
(instance "th23w2" (("assoc_0n" 1) ("mint_0n" 1) "i0_2" "i1_0"))
(instance "th23w2" (("assoc_0n" 0) ("mint_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fa_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 6)
("assoc_0n" 6)
("eqv_0n" 4)
("fsum_0n" 4)
("fcar_0n" 2)
("fext_0n" 2)
("fshar_0n" 1)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("s_1" ("fext_0n" 1) "ci_0" "ci_1" ("fshar_0n" 0)))
(instance "th34w22" ("s_0" ("fext_0n" 0) "ci_1" "ci_0" ("fshar_0n" 0)))
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 0)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 1)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 0)))
(instance "or2" (("fshar_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "or4" (("fext_0n" 1) ("assoc_0n" 1) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "or4" (("fext_0n" 0) ("assoc_0n" 0) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "or4" (("fcar_0n" 1) ("assoc_0n" 4) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "or4" (("fcar_0n" 0) ("assoc_0n" 0) ("assoc_0n" 1) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "or3" (("fsum_0n" 3) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 2)))
(instance "or3" (("fsum_0n" 2) ("assoc_0n" 1) ("eqv_0n" 1) ("eqv_0n" 3)))
(instance "or2" (("fsum_0n" 1) ("assoc_0n" 0) ("assoc_0n" 5)))
(instance "or2" (("fsum_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "c2" (("eqv_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("eqv_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("eqv_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("eqv_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" (("assoc_0n" 5) ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23w2" (("assoc_0n" 4) ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23w2" (("assoc_0n" 3) ("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("assoc_0n" 2) ("mint_0n" 2) "i0_3" "i1_0"))
(instance "th23w2" (("assoc_0n" 1) ("mint_0n" 1) "i0_2" "i1_0"))
(instance "th23w2" (("assoc_0n" 0) ("mint_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fs"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("fsum_0n" 4)
("fcar_0n" 2)
("cint_0n" 2)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 3)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 0)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 0)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 1)))
(instance "or3" (("fcar_0n" 1) ("mint_0n" 7) ("mint_0n" 11) ("cint_0n" 1)))
(instance "or3" (("fcar_0n" 0) ("mint_0n" 13) ("mint_0n" 14) ("cint_0n" 0)))
(instance "or4" (("cint_0n" 1) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "or4" (("cint_0n" 0) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "or4" (("fsum_0n" 3) ("mint_0n" 1) ("mint_0n" 6) ("mint_0n" 11) ("mint_0n" 12)))
(instance "or4" (("fsum_0n" 2) ("mint_0n" 2) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 13)))
(instance "or4" (("fsum_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 9) ("mint_0n" 14)))
(instance "or4" (("fsum_0n" 0) ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 6)))
(instance "or2" ("sum_3" "co_0" ("mint_0n" 6)))
(instance "or2" ("sum_2" ("mint_0n" 4) ("mint_0n" 5)))
(instance "or2" ("sum_1" ("mint_0n" 2) ("mint_0n" 3)))
(instance "or2" ("sum_0" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 4)
)
(instances
(instance "or4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 3)))
(instance "or2" ("sum_3" "co_0" ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_3" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
(instance "th23w2" ("sum_2" ("mint_0n" 2) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_2" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_1"))
(instance "th23w2" ("sum_0" ("mint_0n" 0) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or3" ("s_1" "sum_3" "sum_2" ("mint_0n" 3)))
(instance "or2" ("s_0" "sum_0" ("mint_0n" 2)))
(instance "or4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 6)))
(instance "or2" ("sum_3" "co_0" ("mint_0n" 6)))
(instance "or2" ("sum_2" ("mint_0n" 4) ("mint_0n" 5)))
(instance "or2" ("sum_1" ("mint_0n" 2) ("mint_0n" 3)))
(instance "or2" ("sum_0" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 5)
)
(instances
(instance "or3" ("s_1" "sum_3" "sum_2" ("mint_0n" 3)))
(instance "or2" ("s_0" "sum_0" ("mint_0n" 2)))
(instance "or4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 4)))
(instance "or2" ("sum_3" "co_0" ("mint_0n" 4)))
(instance "c2" (("mint_0n" 4) "i0_3" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
(instance "or2" ("sum_2" ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_2" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_1"))
(instance "th23w2" ("sum_0" ("mint_0n" 0) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 1)
)
(instances
(instance "or4" ("co_1" ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or4" ("co_0" ("mint_0n" 0) ("sopint_0n" 0) "sum_2" "sum_3"))
(instance "or4" ("sum_3" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or4" ("sum_2" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "or3" ("sum_1" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "or3" ("sum_0" ("mint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 3)
("sumint_0n" 6)
("carint_0n" 5)
)
(instances
(instance "th23w2" ("co_1" ("carint_0n" 3) ("carint_0n" 4) "ci_1"))
(instance "or3" (("carint_0n" 4) ("mint_0n" 0) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("carint_0n" 3) ("mint_0n" 0) "ci_0"))
(instance "or3" ("co_0" ("carint_0n" 2) "sum_2" "sum_3"))
(instance "th23w2" (("carint_0n" 2) ("carint_0n" 1) ("carint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 1) ("carint_0n" 0) ("sopint_0n" 1) "ci_0"))
(instance "c2" (("carint_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 4) ("sumint_0n" 5) "ci_0"))
(instance "or2" (("sumint_0n" 5) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("sumint_0n" 4) ("sopint_0n" 2) "ci_1"))
(instance "th23w2" ("sum_2" ("sumint_0n" 3) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sumint_0n" 2) "ci_1"))
(instance "or2" (("sumint_0n" 2) ("sopint_0n" 0) ("mint_0n" 3)))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("mint_0n" 4) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 0) "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 2) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_3" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or2" ("s_1" ("sopint_0n" 2) ("mint_0n" 8)))
(instance "or4" ("s_0" "sum_1" "sum_0" ("sopint_0n" 1) ("mint_0n" 7)))
(instance "or4" ("co_1" ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or4" ("co_0" ("mint_0n" 0) ("sopint_0n" 0) "sum_2" "sum_3"))
(instance "or2" ("sum_3" ("mint_0n" 7) ("sopint_0n" 2)))
(instance "or3" (("sopint_0n" 2) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or2" ("sum_2" ("sopint_0n" 1) ("mint_0n" 8)))
(instance "or3" (("sopint_0n" 1) ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6)))
(instance "or3" ("sum_1" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "or3" ("sum_0" ("mint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 3)
("sumint_0n" 6)
("carint_0n" 5)
("exint_0n" 4)
)
(instances
(instance "th23w2" ("s_1" ("exint_0n" 3) ("mint_0n" 3) "ci_1"))
(instance "c2" (("exint_0n" 3) ("exint_0n" 2) "ci_0"))
(instance "or3" (("exint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "or3" ("s_0" "sum_1" "sum_0" ("exint_0n" 1)))
(instance "th23w2" (("exint_0n" 1) ("exint_0n" 0) ("mint_0n" 2) "ci_0"))
(instance "th23" (("exint_0n" 0) "ci_1" ("sopint_0n" 1) ("mint_0n" 2)))
(instance "th23w2" ("co_1" ("carint_0n" 3) ("carint_0n" 4) "ci_1"))
(instance "or3" (("carint_0n" 4) ("mint_0n" 0) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("carint_0n" 3) ("mint_0n" 0) "ci_0"))
(instance "or3" ("co_0" ("carint_0n" 2) "sum_2" "sum_3"))
(instance "th23w2" (("carint_0n" 2) ("carint_0n" 1) ("carint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 1) ("carint_0n" 0) ("sopint_0n" 1) "ci_0"))
(instance "c2" (("carint_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 4) ("sumint_0n" 5) "ci_0"))
(instance "or2" (("sumint_0n" 5) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("sumint_0n" 4) ("sopint_0n" 2) "ci_1"))
(instance "th23w2" ("sum_2" ("sumint_0n" 3) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sumint_0n" 2) "ci_1"))
(instance "or2" (("sumint_0n" 2) ("sopint_0n" 0) ("mint_0n" 4)))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("mint_0n" 5) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 0) "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "or2" (("sopint_0n" 2) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_3" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 1)
)
(instances
(instance "or3" ("co_1" ("sopint_0n" 0) "sum_0" "sum_1"))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or4" ("co_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "or4" ("sum_3" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 15)))
(instance "or4" ("sum_2" ("mint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" ("sum_1" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or4" ("sum_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 4)
("sumint_0n" 4)
("carint_0n" 2)
)
(instances
(instance "th23w2" ("co_1" ("carint_0n" 1) ("mint_0n" 1) "ci_0"))
(instance "th23" (("carint_0n" 1) ("sopint_0n" 3) ("mint_0n" 1) "ci_1"))
(instance "th23w2" ("co_0" ("carint_0n" 0) ("mint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 0) ("sopint_0n" 1) ("mint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_3" ("sumint_0n" 3) ("sopint_0n" 0) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_2" ("sumint_0n" 2) ("sopint_0n" 3) "ci_1"))
(instance "c2" (("sumint_0n" 2) ("sopint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sopint_0n" 2) "ci_1"))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 3) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 4) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "or2" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "or3" ("s_1" ("sopint_0n" 1) "sum_2" "sum_3"))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or4" ("s_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "or3" ("co_1" ("sopint_0n" 0) "sum_0" "sum_1"))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or4" ("co_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "or4" ("sum_3" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 15)))
(instance "or4" ("sum_2" ("mint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" ("sum_1" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or4" ("sum_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 4)
("sumint_0n" 4)
("carint_0n" 2)
("exint_0n" 3)
)
(instances
(instance "or3" ("s_1" "sum_2" "sum_3" ("exint_0n" 2)))
(instance "th23w2" (("exint_0n" 2) ("exint_0n" 1) ("mint_0n" 4) "ci_1"))
(instance "th23" (("exint_0n" 1) "ci_0" ("sopint_0n" 3) ("mint_0n" 4)))
(instance "th23w2" ("s_0" ("exint_0n" 0) ("mint_0n" 3) "ci_0"))
(instance "th23" (("exint_0n" 0) "ci_1" ("sopint_0n" 1) ("mint_0n" 3)))
(instance "th23w2" ("co_1" ("carint_0n" 1) ("mint_0n" 1) "ci_0"))
(instance "th23" (("carint_0n" 1) ("sopint_0n" 3) ("mint_0n" 1) "ci_1"))
(instance "th23w2" ("co_0" ("carint_0n" 0) ("mint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 0) ("sopint_0n" 1) ("mint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_3" ("sumint_0n" 3) ("sopint_0n" 0) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_2" ("sumint_0n" 2) ("sopint_0n" 3) "ci_1"))
(instance "c2" (("sumint_0n" 2) ("sopint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sopint_0n" 2) "ci_1"))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 3) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "or2" (("sopint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "or2" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 15)
("sopint_0n" 2)
)
(instances
(instance "or3" ("q0_2" ("mint_0n" 10) ("mint_0n" 11) ("mint_0n" 14)))
(instance "or3" ("q0_1" ("mint_0n" 5) ("mint_0n" 7) ("mint_0n" 13)))
(instance "or3" ("q0_0" ("mint_0n" 12) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 4) ("mint_0n" 6) ("mint_0n" 8) ("mint_0n" 9)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" ("q0_3" "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_3" "i0_3" "i1_3"))
(instance "th23w2" ("q0_2" ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23" (("mint_0n" 5) "i0_2" "i1_2" "i1_3"))
(instance "th23w2" ("q0_1" ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23" (("mint_0n" 4) "i0_1" "i1_1" "i1_3"))
(instance "th23w2" ("q0_0" ("sopint_0n" 0) "i0_3" "i1_0"))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_1" "i1_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_0" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 15)
("sopint_0n" 2)
)
(instances
(instance "or3" ("q0_3" ("mint_0n" 14) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 10) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "or3" ("q0_2" ("mint_0n" 1) ("mint_0n" 7) ("mint_0n" 9)))
(instance "or3" ("q0_1" ("mint_0n" 0) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 11) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 7) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
(instance "c2" ("q0_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_3" ("sopint_0n" 0) "i0_0" "i1_3"))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "th23" (("mint_0n" 5) "i0_3" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 4) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_1" "i1_3"))
(instance "th23" (("mint_0n" 2) "i0_1" "i1_2" "i1_3"))
(instance "th23w2" ("q0_2" ("mint_0n" 1) "i0_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_2"))
(instance "th23w2" ("q0_1" ("mint_0n" 0) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
(instance "c2" ("q0_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 16)
)
(instances
(instance "or4" ("q0_3" ("mint_0n" 3) ("mint_0n" 6) ("mint_0n" 9) ("mint_0n" 12)))
(instance "or4" ("q0_2" ("mint_0n" 2) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 13)))
(instance "or4" ("q0_1" ("mint_0n" 1) ("mint_0n" 4) ("mint_0n" 11) ("mint_0n" 14)))
(instance "or4" ("q0_0" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 8)
)
(instances
(instance "or2" ("q0_3" ("sopint_0n" 6) ("sopint_0n" 7)))
(instance "th23w2" (("sopint_0n" 7) ("mint_0n" 7) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_2"))
(instance "th23w2" (("sopint_0n" 6) ("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 6) "i0_0" "i1_3"))
(instance "or2" ("q0_2" ("sopint_0n" 4) ("sopint_0n" 5)))
(instance "th23w2" (("sopint_0n" 5) ("mint_0n" 5) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_3"))
(instance "th23w2" (("sopint_0n" 4) ("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_2"))
(instance "or2" ("q0_1" ("sopint_0n" 2) ("sopint_0n" 3)))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 3) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_3"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "or2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or4" ("q0_1" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "or3" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "or4" (("sopint_0n" 2) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 9)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 2)
)
(instances
(instance "or2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 5) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 4) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_0"))
(instance "or4" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th34w2" (("mint_0n" 3) "i0_3" "i1_1" "i1_1" "i1_2"))
(instance "th34w2" (("mint_0n" 2) "i0_2" "i1_0" "i1_1" "i1_3"))
(instance "th34w2" (("mint_0n" 1) "i0_1" "i1_0" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 0) "i0_0" "i1_1" "i1_2" "i1_3"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 0) ("mint_0n" 3)))
(instance "or3" ("q0_0" ("mint_0n" 1) ("mint_0n" 2) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_1" ("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_0"))
(instance "or2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_2" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or3" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "or4" (("sopint_0n" 2) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 9)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "or4" ("q0_0" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 2)
)
(instances
(instance "or4" ("q0_1" ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "th34w2" (("mint_0n" 5) "i0_3" "i1_1" "i1_1" "i1_2"))
(instance "th34w2" (("mint_0n" 4) "i0_2" "i1_0" "i1_1" "i1_3"))
(instance "th34w2" (("mint_0n" 3) "i0_1" "i1_0" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 2) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "or2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or3" ("q0_1" ("mint_0n" 1) ("mint_0n" 2) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "or2" ("q0_0" ("mint_0n" 0) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 2)
)
(instances
(instance "or2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "or3" ("q0_2" ("sopint_0n" 1) ("mint_0n" 7) ("mint_0n" 11)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "or4" ("q0_1" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "or3" ("q0_0" ("sopint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "or3" ("q0_2" ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 6) "i0_1" "i1_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "or2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 4) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_0"))
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th34w2" (("mint_0n" 2) "i0_3" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 0) ("mint_0n" 2)))
(instance "or2" ("q0_0" ("mint_0n" 6) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_0"))
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ineq_sgn_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 0) ("mint_0n" 2)))
(instance "or2" ("q0_2" ("mint_0n" 6) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ineq_sgn_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "or3" ("q0_2" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th23" (("mint_0n" 3) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or3" ("q0_1" ("sopint_0n" 2) ("mint_0n" 7) ("mint_0n" 11)))
(instance "or4" (("sopint_0n" 2) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "or4" ("q0_0" ("mint_0n" 14) ("mint_0n" 15) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12) ("mint_0n" 13)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 8)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or3" (("q0__1_0n" 0) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 6) "i0_1" "i1_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "or3" ("q0_0" ("mint_0n" 3) ("mint_0n" 4) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 4) "i0_3" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 3) "i0_3" "i1_0" "i1_1"))
(instance "th34w2" (("mint_0n" 2) "i0_2" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_1" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or3" ("q0_1" ("sopint_0n" 2) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" (("sopint_0n" 2) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "or4" ("q0_0" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 10)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or3" ("q0_1" ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_3" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 6) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_0"))
(instance "or3" ("q0_0" ("mint_0n" 3) ("mint_0n" 4) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 4) "i0_3" "i1_3"))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 2) "i0_1" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 1) "i0_0" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "or4" ("q0_0" ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "th23w2" ("q0_0" ("sopint_0n" 0) "i0_0" "i1_0"))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 7) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6)))
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_1" ("sopint_0n" 0) "i0_1" "i1_0"))
(instance "or2" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
)
(instances
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_0" "i1_0"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" ("q0_1" "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_1" "i1_0"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_oot_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
)
(instances
(instance "or3" ("q0_1" ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_oot_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q0_1" ("mint_0n" 1) "i0_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_1" "i1_1" "i1_2"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_0"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oot_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 9)
)
(instances
(instance "or4" ("q0_2" ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "or4" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 6) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_2"))
(instance "c2" ("q0_1" "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oot_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q0_2" ("mint_0n" 1) "i0_1" "i1_2"))
(instance "th34w2" (("mint_0n" 1) "i0_2" "i1_0" "i1_1" "i1_2"))
(instance "c2" ("q0_1" "i0_1" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_0"))
(instance "th34w2" (("mint_0n" 0) "i0_0" "i1_0" "i1_1" "i1_2"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
)
(instances
(instance "ao22" ("in_a" "in_0" "out_0" "in_1" "out_1"))
(instance "nor2" ("out_0" "in_1" "out_1"))
(instance "nor2" ("out_1" "in_0" "out_0"))
)
(attributes (simulation-initialise ("out_0" 1)) (cell-type "helper"))
)
(circuit "dr_spacer_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("phase_one_0n" 2)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "or2" ("in_a" ("phase_one_0n" 0) ("phase_one_0n" 1)))
(instance "or2" (("outcomp_0n" 0) "out_0" "out_1"))
(instance "or2" (("incomp_0n" 0) "in_0" "in_1"))
(instance "nor3" ("out_1" ("incomp_0n" 0) ("phase_one_0n" 1) "out_0"))
(instance "nor3" ("out_0" ("incomp_0n" 0) ("phase_one_0n" 0) "out_1"))
(instance "nor3" (("phase_one_0n" 1) ("outcomp_0n" 0) "in_1" ("phase_one_0n" 0)))
(instance "nor3" (("phase_one_0n" 0) ("outcomp_0n" 0) "in_0" ("phase_one_0n" 1)))
)
(attributes (simulation-initialise ("out_0" 1)) (cell-type "helper"))
)
(circuit "dr_ncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("phase_one_0n" 2)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "or2" ("in_a" ("phase_one_0n" 0) ("phase_one_0n" 1)))
(instance "nor2" (("outcomp_0n" 0) "out_0" "out_1"))
(instance "nor2" (("incomp_0n" 0) "in_0" "in_1"))
(instance "c2" ("out_1" ("phase_one_0n" 1) ("incomp_0n" 0)))
(instance "c2" ("out_0" ("phase_one_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("phase_one_0n" 1) "in_1" ("outcomp_0n" 0)))
(instance "c2" (("phase_one_0n" 0) "in_0" ("outcomp_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_tncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_r" input 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("write_sel_0n" 2)
("phase_one_0n" 2)
("phase_two_0n" 2)
("read_store_0n" 2)
("wrcomp_0n" 1)
("incomp_0n" 1)
("pocomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "c2" ("in_a" ("pocomp_0n" 0) ("wrcomp_0n" 0)))
(instance "or2" (("pocomp_0n" 0) ("phase_one_0n" 0) ("phase_one_0n" 1)))
(instance "nor2" (("outcomp_0n" 0) ("phase_two_0n" 0) ("phase_two_0n" 1)))
(instance "nor2" (("incomp_0n" 0) ("write_sel_0n" 0) ("write_sel_0n" 1)))
(instance "or2" (("wrcomp_0n" 0) "in_0" "in_1"))
(instance "c2" ("out_1" ("read_store_0n" 1) ("pocomp_0n" 0)))
(instance "c2" ("out_0" ("read_store_0n" 0) ("pocomp_0n" 0)))
(instance "c2" (("read_store_0n" 1) ("phase_two_0n" 1) "out_r"))
(instance "c2" (("read_store_0n" 0) ("phase_two_0n" 0) "out_r"))
(instance "c2" (("phase_two_0n" 1) ("phase_one_0n" 1) ("incomp_0n" 0)))
(instance "c2" (("phase_two_0n" 0) ("phase_one_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("phase_one_0n" 1) ("write_sel_0n" 1) ("outcomp_0n" 0)))
(instance "c2" (("phase_one_0n" 0) ("write_sel_0n" 0) ("outcomp_0n" 0)))
(instance "or2" (("write_sel_0n" 1) "in_1" ("read_store_0n" 1)))
(instance "or2" (("write_sel_0n" 0) "in_0" ("read_store_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("inp__nor_0n" 4)
("cross__na_0n" 2)
("nor__latch_0n" 4)
("group__na_0n" 4)
("ack__na_0n" 2)
("ph__4_0n" 4)
)
(instances
(instance "or2" ("in_a" ("ack__na_0n" 0) ("ack__na_0n" 1)))
(instance "nand2" (("ack__na_0n" 1) ("group__na_0n" 2) ("group__na_0n" 3)))
(instance "nand2" (("ack__na_0n" 0) ("group__na_0n" 0) ("group__na_0n" 1)))
(instance "nand2" (("group__na_0n" 3) "in_3" ("nor__latch_0n" 3)))
(instance "nand2" (("group__na_0n" 2) "in_2" ("nor__latch_0n" 2)))
(instance "nand2" (("group__na_0n" 1) "in_1" ("nor__latch_0n" 1)))
(instance "nand2" (("group__na_0n" 0) "in_0" ("nor__latch_0n" 0)))
(instance "nor2" (("nor__latch_0n" 3) ("cross__na_0n" 0) "out_2"))
(instance "nor2" (("nor__latch_0n" 2) ("cross__na_0n" 0) "out_3"))
(instance "nor2" (("nor__latch_0n" 1) ("cross__na_0n" 1) "out_0"))
(instance "nor2" (("nor__latch_0n" 0) ("cross__na_0n" 1) "out_1"))
(instance "nand2" (("cross__na_0n" 1) ("inp__nor_0n" 2) ("inp__nor_0n" 3)))
(instance "nand2" (("cross__na_0n" 0) ("inp__nor_0n" 0) ("inp__nor_0n" 1)))
(instance "inv" ("out_3" ("inp__nor_0n" 3)))
(instance "inv" ("out_2" ("inp__nor_0n" 2)))
(instance "inv" ("out_1" ("inp__nor_0n" 1)))
(instance "inv" ("out_0" ("inp__nor_0n" 0)))
(instance "nor2" (("inp__nor_0n" 3) "in_3" ("nor__latch_0n" 3)))
(instance "nor2" (("inp__nor_0n" 2) "in_2" ("nor__latch_0n" 2)))
(instance "nor2" (("inp__nor_0n" 1) "in_1" ("nor__latch_0n" 1)))
(instance "nor2" (("inp__nor_0n" 0) "in_0" ("nor__latch_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("_phase_one_0n" 4)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "or4" ("in_a" ("_phase_one_0n" 0) ("_phase_one_0n" 1) ("_phase_one_0n" 2) ("_phase_one_0n" 3)))
(instance "nor4" (("outcomp_0n" 0) "out_0" "out_1" "out_2" "out_3"))
(instance "nor4" (("incomp_0n" 0) "in_0" "in_1" "in_2" "in_3"))
(instance "c2" ("out_3" ("_phase_one_0n" 3) ("incomp_0n" 0)))
(instance "c2" ("out_2" ("_phase_one_0n" 2) ("incomp_0n" 0)))
(instance "c2" ("out_1" ("_phase_one_0n" 1) ("incomp_0n" 0)))
(instance "c2" ("out_0" ("_phase_one_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 3) "in_3" ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 2) "in_2" ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 1) "in_1" ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 0) "in_0" ("outcomp_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_tncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_r" input 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("_write_sel_0n" 4)
("_phase_one_0n" 4)
("_phase_two_0n" 4)
("_read_store_0n" 4)
("wrcomp_0n" 1)
("incomp_0n" 1)
("pocomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "c2" ("in_a" ("pocomp_0n" 0) ("wrcomp_0n" 0)))
(instance "or4" (("pocomp_0n" 0) ("_phase_one_0n" 0) ("_phase_one_0n" 1) ("_phase_one_0n" 2) ("_phase_one_0n" 3)))
(instance "nor4" (("outcomp_0n" 0) ("_phase_two_0n" 0) ("_phase_two_0n" 1) ("_phase_two_0n" 2) ("_phase_two_0n" 3)))
(instance "nor4" (("incomp_0n" 0) ("_write_sel_0n" 0) ("_write_sel_0n" 1) ("_write_sel_0n" 2) ("_write_sel_0n" 3)))
(instance "or4" (("wrcomp_0n" 0) "in_0" "in_1" "in_2" "in_3"))
(instance "c2" ("out_3" ("_read_store_0n" 3) ("pocomp_0n" 0)))
(instance "c2" ("out_2" ("_read_store_0n" 2) ("pocomp_0n" 0)))
(instance "c2" ("out_1" ("_read_store_0n" 1) ("pocomp_0n" 0)))
(instance "c2" ("out_0" ("_read_store_0n" 0) ("pocomp_0n" 0)))
(instance "c2" (("_read_store_0n" 3) ("_phase_two_0n" 3) "out_r"))
(instance "c2" (("_read_store_0n" 2) ("_phase_two_0n" 2) "out_r"))
(instance "c2" (("_read_store_0n" 1) ("_phase_two_0n" 1) "out_r"))
(instance "c2" (("_read_store_0n" 0) ("_phase_two_0n" 0) "out_r"))
(instance "c2" (("_phase_two_0n" 3) ("_phase_one_0n" 3) ("incomp_0n" 0)))
(instance "c2" (("_phase_two_0n" 2) ("_phase_one_0n" 2) ("incomp_0n" 0)))
(instance "c2" (("_phase_two_0n" 1) ("_phase_one_0n" 1) ("incomp_0n" 0)))
(instance "c2" (("_phase_two_0n" 0) ("_phase_one_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 3) ("_write_sel_0n" 3) ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 2) ("_write_sel_0n" 2) ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 1) ("_write_sel_0n" 1) ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 0) ("_write_sel_0n" 0) ("outcomp_0n" 0)))
(instance "or2" (("_write_sel_0n" 3) "in_3" ("_read_store_0n" 3)))
(instance "or2" (("_write_sel_0n" 2) "in_2" ("_read_store_0n" 2)))
(instance "or2" (("_write_sel_0n" 1) "in_1" ("_read_store_0n" 1)))
(instance "or2" (("_write_sel_0n" 0) "in_0" ("_read_store_0n" 0)))
)
(attributes (cell-type "helper"))
)
balsa-tech-xilinx/xilinx/.svn/text-base/balsa-cells-caps.net.svn-base0000444003172000014400000042514310212061546025777 0ustar tomswapt00000000000000;;; `balsa-cells-caps.net'
;;; xilinx Balsa helper cells
;;; Created: Wed Jun 2 13:19:59 BST 2004
;;; By: Sam Taylor (Linux)
;;; With net-net version: 20031009
(circuit "mutex1"
(ports
("q0" output 1)
("q1" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "NOR2" (("int_0n" 0) "i0" ("int_0n" 1)))
(instance "NOR2" (("int_0n" 1) "i1" ("int_0n" 1)))
(instance "NOR3" ("q0" ("int_0n" 0) ("int_0n" 0) ("int_0n" 0)))
(instance "NOR3" ("q1" ("int_0n" 1) ("int_0n" 1) ("int_0n" 1)))
)
(attributes (cell-type "helper"))
)
(circuit "ao22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "OR2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "AND2" (("int_0n" 1) "i2" "i3"))
(instance "AND2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "aoi22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "NOR2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "AND2" (("int_0n" 1) "i2" "i3"))
(instance "AND2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "ao222"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
("i4" input 1)
("i5" input 1)
)
(nets
("int_0n" 3)
)
(instances
(instance "OR3" ("q" ("int_0n" 0) ("int_0n" 1) ("int_0n" 2)))
(instance "AND2" (("int_0n" 2) "i4" "i5"))
(instance "AND2" (("int_0n" 1) "i2" "i3"))
(instance "AND2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "aoi222"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
("i4" input 1)
("i5" input 1)
)
(nets
("int_0n" 3)
)
(instances
(instance "NOR3" ("q" ("int_0n" 0) ("int_0n" 1) ("int_0n" 2)))
(instance "AND2" (("int_0n" 2) "i4" "i5"))
(instance "AND2" (("int_0n" 1) "i2" "i3"))
(instance "AND2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "srff"
(ports
("s" input 1)
("r" input 1)
("q" output 1)
("nq" output 1)
)
(nets
)
(instances
(instance "NOR2" ("nq" "q" "s"))
(instance "NOR2" ("q" "nq" "r"))
)
(attributes (simulation-initialise ("q" 0)) (cell-type "helper"))
)
(circuit "mux2"
(ports
("q" output 1)
("d0" input 1)
("d1" input 1)
("sel" input 1)
)
(nets
("int_0n" 2)
("nsel_0n" 1)
)
(instances
(instance "NAND2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "NAND2" (("int_0n" 1) "d1" "sel"))
(instance "NAND2" (("int_0n" 0) "d0" ("nsel_0n" 0)))
(instance "INV" (("nsel_0n" 0) "sel"))
)
(attributes (cell-type "helper"))
)
(circuit "nmux2"
(ports
("q" output 1)
("d0" input 1)
("d1" input 1)
("sel" input 1)
)
(nets
("int_0n" 2)
("nsel_0n" 1)
("nq_0n" 1)
)
(instances
(instance "INV" ("q" ("nq_0n" 0)))
(instance "NAND2" (("nq_0n" 0) ("int_0n" 0) ("int_0n" 1)))
(instance "NAND2" (("int_0n" 1) "d1" "sel"))
(instance "NAND2" (("int_0n" 0) "d0" ("nsel_0n" 0)))
(instance "INV" (("nsel_0n" 0) "sel"))
)
(attributes (cell-type "helper"))
)
(circuit "balsa_fa"
(ports
("nStart" input 1)
("A" input 1)
("B" input 1)
("nCVi" input 1)
("Ci" input 1)
("nCVo" output 1)
("Co" output 1)
("sum" output 1)
)
(nets
("start_0n" 1)
("ha_0n" 1)
("cv_0n" 1)
)
(instances
(instance "XOR2" ("sum" ("ha_0n" 0) "Ci"))
(instance "XOR2" (("ha_0n" 0) "A" "B"))
(instance "mux2" ("Co" "A" "Ci" ("ha_0n" 0)))
(instance "nmux2" ("nCVo" ("start_0n" 0) ("cv_0n" 0) ("ha_0n" 0)))
(instance "NOR2" (("cv_0n" 0) "nStart" "nCVi"))
(instance "INV" (("start_0n" 0) "nStart"))
)
(attributes (cell-type "helper"))
)
(circuit "c2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
)
(instances
(instance "ao222" ("q" "i0" "i1" "i0" "q" "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "c3"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("qint_0n" 1)
)
(instances
(instance "c2" ("q" "i2" ("qint_0n" 0)))
(instance "c2" (("qint_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "nc2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("nq_0n" 1)
)
(instances
(instance "aoi222" ("q" "i0" "i1" "i0" ("nq_0n" 0) "i1" ("nq_0n" 0)))
(instance "INV" (("nq_0n" 0) "q"))
)
(attributes (cell-type "helper"))
)
(circuit "nc2p"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("nq_0n" 1)
)
(instances
(instance "aoi22" ("q" "i0" "i1" "i0" ("nq_0n" 0)))
(instance "INV" (("nq_0n" 0) "q"))
)
(attributes (cell-type "helper"))
)
(circuit "demux2"
(ports
("i" input 1)
("o0" output 1)
("o1" output 1)
("s" input 1)
)
(nets
("ns_0n" 1)
)
(instances
(instance "AND2" ("o1" "i" "s"))
(instance "AND2" ("o0" "i" ("ns_0n" 0)))
(instance "INV" (("ns_0n" 0) "s"))
)
(attributes (cell-type "helper"))
)
(circuit "selem"
(ports
("Ar" input 1)
("Aa" output 1)
("Br" output 1)
("Ba" input 1)
)
(nets
("s_0n" 1)
)
(instances
(instance "nc2p" (("s_0n" 0) "Ar" "Ba"))
(instance "NOR2" ("Aa" "Ba" ("s_0n" 0)))
(instance "AND2" ("Br" "Ar" ("s_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "th22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("qint_0n" 3)
)
(instances
(instance "OR3" ("q" ("qint_0n" 0) ("qint_0n" 1) ("qint_0n" 2)))
(instance "AND2" (("qint_0n" 2) "i1" "q"))
(instance "AND2" (("qint_0n" 1) "i0" "q"))
(instance "AND2" (("qint_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "th33"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("qint_0n" 2)
)
(instances
(instance "OR2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "OR3" (("qint_0n" 1) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "AND2" (("qint_0n" 0) "i1" "i2"))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th23"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 2)
("qint_0n" 2)
("sinti_0n" 1)
)
(instances
(instance "OR2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "OR2" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1)))
(instance "AND2" (("sint_0n" 1) "i0" ("sinti_0n" 0)))
(instance "AND2" (("sint_0n" 0) "i1" "i2"))
(instance "OR2" (("sinti_0n" 0) "i1" "i2"))
(instance "OR3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th23w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 2)
("sint_0n" 1)
)
(instances
(instance "OR4" ("q" "i0" ("hint_0n" 0) ("hint_0n" 1) ("sint_0n" 0)))
(instance "AND2" (("sint_0n" 0) "i1" "i2"))
(instance "AND2" (("hint_0n" 1) "i2" "q"))
(instance "AND2" (("hint_0n" 0) "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 4)
("sint_0n" 6)
("qint_0n" 3)
)
(instances
(instance "OR3" ("q" ("qint_0n" 0) ("qint_0n" 1) ("qint_0n" 2)))
(instance "OR3" (("qint_0n" 2) ("sint_0n" 3) ("sint_0n" 4) ("sint_0n" 5)))
(instance "OR3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "AND2" (("sint_0n" 5) "i2" "i3"))
(instance "AND2" (("sint_0n" 4) "i1" "i3"))
(instance "AND2" (("sint_0n" 3) "i1" "i2"))
(instance "AND2" (("sint_0n" 2) "i0" "i3"))
(instance "AND2" (("sint_0n" 1) "i0" "i2"))
(instance "AND2" (("sint_0n" 0) "i0" "i1"))
(instance "OR4" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2) ("hint_0n" 3)))
(instance "AND2" (("hint_0n" 3) "i3" "q"))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 3)
("qint_0n" 2)
)
(instances
(instance "OR3" ("q" ("qint_0n" 0) ("qint_0n" 1) "i0"))
(instance "OR3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "AND2" (("sint_0n" 2) "i2" "i3"))
(instance "AND2" (("sint_0n" 1) "i1" "i3"))
(instance "AND2" (("sint_0n" 0) "i1" "i2"))
(instance "OR3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "AND2" (("hint_0n" 2) "i3" "q"))
(instance "AND2" (("hint_0n" 1) "i2" "q"))
(instance "AND2" (("hint_0n" 0) "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24w22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 2)
("sint_0n" 1)
("qint_0n" 1)
)
(instances
(instance "OR3" ("q" "i0" "i1" ("qint_0n" 0)))
(instance "OR3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("sint_0n" 0)))
(instance "AND2" (("sint_0n" 0) "i2" "i3"))
(instance "AND2" (("hint_0n" 1) "i3" "q"))
(instance "AND2" (("hint_0n" 0) "i2" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th33w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 1)
("qint_0n" 2)
)
(instances
(instance "OR2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "OR3" (("qint_0n" 2) ("sint_0n" 3) ("sint_0n" 4) ("sint_0n" 5)))
(instance "OR3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "AND2" (("qint_0n" 1) "i0" ("sint_0n" 0)))
(instance "OR2" (("sint_0n" 0) "i1" "i2"))
(instance "OR3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th34"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 4)
("sint_0n" 2)
("qint_0n" 2)
("sinti_0n" 2)
)
(instances
(instance "OR2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "OR2" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1)))
(instance "AND3" (("sint_0n" 1) "i1" "i3" ("sinti_0n" 1)))
(instance "OR2" (("sinti_0n" 1) "i0" "i2"))
(instance "AND3" (("sint_0n" 0) "i0" "i2" ("sinti_0n" 0)))
(instance "OR2" (("sinti_0n" 0) "i1" "i3"))
(instance "OR4" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2) ("hint_0n" 3)))
(instance "AND2" (("hint_0n" 3) "i3" "q"))
(instance "AND2" (("hint_0n" 2) "i2" "q"))
(instance "AND2" (("hint_0n" 1) "i1" "q"))
(instance "AND2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th34w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q" ("mint_0n" 0) ("mint_0n" 1) "i0"))
(instance "OR3" (("mint_0n" 1) "i1" "i2" "i3"))
(instance "c3" (("mint_0n" 0) "i1" "i2" "i3"))
)
(attributes (cell-type "helper"))
)
(circuit "th34w22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "th23" ("q" ("mint_0n" 0) "i0" "i1"))
(instance "OR2" (("mint_0n" 0) "i2" "i3"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "OR3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
(instance "c2" ("q_1" "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
(instance "OR3" ("q_1" "GND" ("n3_0n" 0) "GND"))
(instance "c2" (("n3_0n" 0) "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "c2" ("q_1" "i0_1" "i1_1"))
(instance "th34w22" ("q_0" "i0_0" "i1_0" "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "c2" ("q_0" "i0_0" "i1_0"))
(instance "OR3" ("q_1" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("q_0" "GND" ("n3_0n" 0) "GND"))
(instance "c2" (("n3_0n" 0) "i0_0" "i1_0"))
(instance "OR3" ("q_1" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "th34w22" ("q_1" "i0_1" "i1_1" "i0_0" "i1_0"))
(instance "c2" ("q_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_nor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "c2" ("q_1" "i0_0" "i1_0"))
(instance "OR3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_nor2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "c2" ("q_1" "i0_0" "i1_0"))
(instance "th34w22" ("q_0" "i0_1" "i1_1" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR2" ("q_0" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "OR2" ("q_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_xor2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "th23w2" ("q_1" ("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "th23w2" ("q_0" ("n0_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2_bal" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2_bal" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2_ncl" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2_ncl" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21_bal" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2_bal" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21_ncl" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2_ncl" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_mux2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("s_0" input 1)
("s_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR2" ("q_0" ("n0_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "s_0" "i0_0"))
(instance "c2" (("n2_0n" 0) "s_1" "i1_0"))
(instance "OR2" ("q_1" ("n1_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n1_0n" 0) "s_0" "i0_1"))
(instance "c2" (("n3_0n" 0) "s_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_mux2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("s_0" input 1)
("s_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "th23w2" ("q_1" ("n1_0n" 0) "s_0" "i0_1"))
(instance "c2" (("n1_0n" 0) "s_1" "i1_1"))
(instance "th23w2" ("q_0" ("n0_0n" 0) "s_0" "i0_0"))
(instance "c2" (("n0_0n" 0) "s_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "OR3" ("co_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_0" ("n0_0n" 0) "co_1"))
(instance "c2" ("co_1" "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("co_1" "GND" ("n3_0n" 0) "GND"))
(instance "OR3" ("co_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_0" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha_ncl"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
)
(instances
(instance "th23w2" ("co_0" "sum_1" "a_0" "b_0"))
(instance "th23w2" ("sum_1" ("n0_0n" 0) "a_1" "b_0"))
(instance "c2" (("n0_0n" 0) "a_0" "b_1"))
(instance "th23w2" ("sum_0" "co_1" "a_0" "b_0"))
(instance "c2" ("co_1" "a_1" "b_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("ha__1_0n" 1)
("ha__0_0n" 1)
("n0__1_0n" 1)
("n0_0n" 1)
)
(instances
(instance "th23w2" ("co_0" "sum_1" "a_0" "b_0"))
(instance "th23w2" ("sum_1" ("n0_0n" 0) "a_1" "b_0"))
(instance "c2" (("n0_0n" 0) "a_0" "b_1"))
(instance "th23w2" ("sum_0" "co_1" "a_0" "b_0"))
(instance "c2" ("co_1" "a_1" "b_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("ha__1_0n" 1)
("ha__0_0n" 1)
("n0__1_0n" 1)
("n0__0_0n" 1)
("n1__1_0n" 1)
("n1__0_0n" 1)
)
(instances
(instance "dr_xor2" (("n0__0_0n" 0) ("n0__1_0n" 0) ("n1__0_0n" 0) ("n1__1_0n" 0) "co_0" "co_1"))
(instance "dr_ha_bal" (("ha__0_0n" 0) ("ha__1_0n" 0) "ci_0" "ci_1" ("n1__0_0n" 0) ("n1__1_0n" 0) "sum_0" "sum_1"))
(instance "dr_ha_bal" ("a_0" "a_1" "b_0" "b_1" ("n0__0_0n" 0) ("n0__1_0n" 0) ("ha__0_0n" 0) ("ha__1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_fa"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("minterm_0n" 8)
)
(instances
(instance "OR4" ("co0" ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4)))
(instance "OR4" ("co1" ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 7)))
(instance "OR4" ("sum0" ("minterm_0n" 0) ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "OR4" ("sum1" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4) ("minterm_0n" 7)))
(instance "c3" (("minterm_0n" 7) "a1" "b1" "ci1"))
(instance "c3" (("minterm_0n" 6) "a1" "b1" "ci0"))
(instance "c3" (("minterm_0n" 5) "a1" "b0" "ci1"))
(instance "c3" (("minterm_0n" 4) "a1" "b0" "ci0"))
(instance "c3" (("minterm_0n" 3) "a0" "b1" "ci1"))
(instance "c3" (("minterm_0n" 2) "a0" "b1" "ci0"))
(instance "c3" (("minterm_0n" 1) "a0" "b0" "ci1"))
(instance "c3" (("minterm_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_fa"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
)
(instances
(instance "th34w2" ("sum1" "co0" "a1" "b1" "ci1"))
(instance "th34w2" ("sum0" "co1" "a0" "b0" "ci0"))
(instance "th23" ("co1" "a1" "b1" "ci1"))
(instance "th23" ("co0" "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("co_1" ("n1_0n" 0) ("n2_0n" 0) ("n3_0n" 0)))
(instance "OR2" ("sum_0" ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_1" "co_0" ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" ("co_0" "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "OR3" ("co_0" "GND" ("n0_0n" 0) "GND"))
(instance "OR3" ("co_1" ("n1_0n" 0) ("n2_0n" 0) ("n3_0n" 0)))
(instance "OR2" ("sum_0" ("n1_0n" 0) ("n2_0n" 0)))
(instance "OR2" ("sum_1" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p_ncl"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "th23w2" ("co_1" "sum_0" "a_0" "b_1"))
(instance "th23w2" ("sum_1" "co_0" "a_1" "b_1"))
(instance "c2" ("co_0" "a_0" "b_0"))
(instance "th23w2" ("sum_0" ("n0_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_1" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_fs"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("minterm_0n" 8)
)
(instances
(instance "OR4" ("co1" ("minterm_0n" 0) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "OR4" ("co0" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3) ("minterm_0n" 7)))
(instance "OR4" ("sum1" ("minterm_0n" 0) ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "OR4" ("sum0" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4) ("minterm_0n" 7)))
(instance "c3" (("minterm_0n" 7) "a1" "b1" "ci1"))
(instance "c3" (("minterm_0n" 6) "a1" "b1" "ci0"))
(instance "c3" (("minterm_0n" 5) "a1" "b0" "ci1"))
(instance "c3" (("minterm_0n" 4) "a1" "b0" "ci0"))
(instance "c3" (("minterm_0n" 3) "a0" "b1" "ci1"))
(instance "c3" (("minterm_0n" 2) "a0" "b1" "ci0"))
(instance "c3" (("minterm_0n" 1) "a0" "b0" "ci1"))
(instance "c3" (("minterm_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_fs"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("cint_0n" 2)
)
(instances
(instance "th23" ("co1" ("cint_0n" 0) "b1" ("ci1_0n" 0)))
(instance "th23" ("co0" ("cint_0n" 1) "b0" ("ci0_0n" 0)))
(instance "th34w2" ("sum1" ("cint_0n" 0) "a1" "b1" "ci1"))
(instance "th34w2" ("sum0" ("cint_0n" 1) "a0" "b0" "ci0"))
(instance "th23" (("cint_0n" 1) "a1" "b1" "ci1"))
(instance "th23" (("cint_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ha"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 4)
)
(instances
(instance "OR3" ("co_1" ("sopint_0n" 0) ("sopint_0n" 2) ("mint_0n" 11)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 3) "sum_3"))
(instance "OR4" ("sum_3" ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR2" ("sum_2" ("sopint_0n" 3) ("mint_0n" 11)))
(instance "OR2" ("sum_1" ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "OR2" ("sum_0" ("mint_0n" 0) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 3) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 10)))
(instance "OR2" (("sopint_0n" 2) ("mint_0n" 6) ("mint_0n" 7)))
(instance "OR2" (("sopint_0n" 1) ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 14) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 13) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 12) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 11) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 9) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 6) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "OR2" ("sum_3" ("mint_0n" 5) ("mint_0n" 6)))
(instance "OR2" ("sum_2" ("mint_0n" 3) ("mint_0n" 4)))
(instance "OR2" ("sum_1" ("mint_0n" 1) ("mint_0n" 2)))
(instance "OR2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 4)
)
(instances
(instance "OR4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "th23w2" ("sum_3" ("mint_0n" 3) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_1"))
(instance "th23w2" ("sum_2" ("mint_0n" 2) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "OR2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR2" ("s_1" ("mint_0n" 4) "sum_3"))
(instance "OR4" ("s_0" ("mint_0n" 0) "sum_1" ("mint_0n" 3) "co_1"))
(instance "OR4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "OR2" ("sum_3" ("mint_0n" 5) ("mint_0n" 6)))
(instance "OR2" ("sum_2" ("mint_0n" 3) ("mint_0n" 4)))
(instance "OR2" ("sum_1" ("mint_0n" 1) ("mint_0n" 2)))
(instance "OR2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR2" ("s_1" ("mint_0n" 3) "sum_3"))
(instance "OR4" ("s_0" ("mint_0n" 0) "sum_1" ("mint_0n" 2) "co_1"))
(instance "OR4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "th23w2" ("sum_3" ("mint_0n" 4) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "OR2" ("sum_2" ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "OR2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("halfsum_0n" 4)
("halfcar_0n" 4)
)
(instances
(instance "dr_xor2" (("halfcar_0n" 0) ("halfcar_0n" 1) ("halfcar_0n" 2) ("halfcar_0n" 3) "co_0" "co_1"))
(instance "oof_dims_ca" (("halfsum_0n" 0) ("halfsum_0n" 1) ("halfsum_0n" 2) ("halfsum_0n" 3) "ci_0" "ci_1" ("halfcar_0n" 2) ("halfcar_0n" 3) "sum_0" "sum_1" "sum_2" "sum_3"))
(instance "oof_ha" ("i0_0" "i0_1" "i0_2" "i0_3" "i1_0" "i1_1" "i1_2" "i1_3" ("halfcar_0n" 0) ("halfcar_0n" 1) ("halfsum_0n" 0) ("halfsum_0n" 1) ("halfsum_0n" 2) ("halfsum_0n" 3)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
)
(instances
(instance "OR4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "OR4" (("carrint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "OR4" (("carrint_0n" 6) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "OR4" (("carrint_0n" 5) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 21) ("minterm_0n" 22)))
(instance "OR4" (("carrint_0n" 4) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "OR4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "OR4" (("carrint_0n" 3) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24)))
(instance "OR4" (("carrint_0n" 2) ("minterm_0n" 9) ("minterm_0n" 10) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR4" (("carrint_0n" 1) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8)))
(instance "OR4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "OR2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "OR4" (("sumint_0n" 7) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "OR4" (("sumint_0n" 6) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "OR4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "OR4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "OR2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "OR4" (("sumint_0n" 3) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "OR4" (("sumint_0n" 2) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "OR2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "OR4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "OR4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fa_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
("overint_0n" 8)
)
(instances
(instance "OR4" ("s_1" ("overint_0n" 4) ("overint_0n" 5) ("overint_0n" 6) ("overint_0n" 7)))
(instance "OR4" (("overint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "OR4" (("overint_0n" 6) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 23) ("minterm_0n" 24)))
(instance "OR4" (("overint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 20)))
(instance "OR4" (("overint_0n" 4) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 12)))
(instance "OR4" ("s_0" ("overint_0n" 0) ("overint_0n" 1) ("overint_0n" 2) ("overint_0n" 3)))
(instance "OR4" (("overint_0n" 3) ("minterm_0n" 19) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "OR4" (("overint_0n" 2) ("minterm_0n" 11) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "OR4" (("overint_0n" 1) ("minterm_0n" 7) ("minterm_0n" 8) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "OR4" (("overint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "OR4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "OR4" (("carrint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "OR4" (("carrint_0n" 6) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "OR4" (("carrint_0n" 5) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 21) ("minterm_0n" 22)))
(instance "OR4" (("carrint_0n" 4) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "OR4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "OR4" (("carrint_0n" 3) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24)))
(instance "OR4" (("carrint_0n" 2) ("minterm_0n" 9) ("minterm_0n" 10) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR4" (("carrint_0n" 1) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8)))
(instance "OR4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "OR2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "OR4" (("sumint_0n" 7) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "OR4" (("sumint_0n" 6) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "OR4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "OR4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "OR2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "OR4" (("sumint_0n" 3) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "OR4" (("sumint_0n" 2) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "OR2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "OR4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "OR4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fs"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
)
(instances
(instance "OR4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "OR4" (("carrint_0n" 7) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 23) ("minterm_0n" 31)))
(instance "OR4" (("carrint_0n" 6) ("minterm_0n" 12) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "OR4" (("carrint_0n" 5) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 7) ("minterm_0n" 11)))
(instance "OR4" (("carrint_0n" 4) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3) ("minterm_0n" 4)))
(instance "OR4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "OR4" (("carrint_0n" 3) ("minterm_0n" 27) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "OR4" (("carrint_0n" 2) ("minterm_0n" 20) ("minterm_0n" 24) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "OR4" (("carrint_0n" 1) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 19)))
(instance "OR4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 8) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "OR2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "OR4" (("sumint_0n" 7) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "OR4" (("sumint_0n" 6) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "OR2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "OR4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "OR4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "OR2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "OR4" (("sumint_0n" 3) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "OR4" (("sumint_0n" 2) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "OR2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "OR4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "OR4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 6)
("assoc_0n" 6)
("eqv_0n" 4)
("fsum_0n" 4)
("fcar_0n" 2)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 0)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 1)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 0)))
(instance "OR4" (("fcar_0n" 1) ("assoc_0n" 4) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "OR4" (("fcar_0n" 0) ("assoc_0n" 0) ("assoc_0n" 1) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "OR3" (("fsum_0n" 3) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 2)))
(instance "OR3" (("fsum_0n" 2) ("assoc_0n" 1) ("eqv_0n" 1) ("eqv_0n" 3)))
(instance "OR2" (("fsum_0n" 1) ("assoc_0n" 0) ("assoc_0n" 5)))
(instance "OR2" (("fsum_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "c2" (("eqv_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("eqv_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("eqv_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("eqv_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" (("assoc_0n" 5) ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23w2" (("assoc_0n" 4) ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23w2" (("assoc_0n" 3) ("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("assoc_0n" 2) ("mint_0n" 2) "i0_3" "i1_0"))
(instance "th23w2" (("assoc_0n" 1) ("mint_0n" 1) "i0_2" "i1_0"))
(instance "th23w2" (("assoc_0n" 0) ("mint_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fa_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 6)
("assoc_0n" 6)
("eqv_0n" 4)
("fsum_0n" 4)
("fcar_0n" 2)
("fext_0n" 2)
("fshar_0n" 1)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("s_1" ("fext_0n" 1) "ci_0" "ci_1" ("fshar_0n" 0)))
(instance "th34w22" ("s_0" ("fext_0n" 0) "ci_1" "ci_0" ("fshar_0n" 0)))
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 0)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 1)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 0)))
(instance "OR2" (("fshar_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "OR4" (("fext_0n" 1) ("assoc_0n" 1) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "OR4" (("fext_0n" 0) ("assoc_0n" 0) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "OR4" (("fcar_0n" 1) ("assoc_0n" 4) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "OR4" (("fcar_0n" 0) ("assoc_0n" 0) ("assoc_0n" 1) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "OR3" (("fsum_0n" 3) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 2)))
(instance "OR3" (("fsum_0n" 2) ("assoc_0n" 1) ("eqv_0n" 1) ("eqv_0n" 3)))
(instance "OR2" (("fsum_0n" 1) ("assoc_0n" 0) ("assoc_0n" 5)))
(instance "OR2" (("fsum_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "c2" (("eqv_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("eqv_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("eqv_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("eqv_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" (("assoc_0n" 5) ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23w2" (("assoc_0n" 4) ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23w2" (("assoc_0n" 3) ("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("assoc_0n" 2) ("mint_0n" 2) "i0_3" "i1_0"))
(instance "th23w2" (("assoc_0n" 1) ("mint_0n" 1) "i0_2" "i1_0"))
(instance "th23w2" (("assoc_0n" 0) ("mint_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fs"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("fsum_0n" 4)
("fcar_0n" 2)
("cint_0n" 2)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 3)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 0)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 0)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 1)))
(instance "OR3" (("fcar_0n" 1) ("mint_0n" 7) ("mint_0n" 11) ("cint_0n" 1)))
(instance "OR3" (("fcar_0n" 0) ("mint_0n" 13) ("mint_0n" 14) ("cint_0n" 0)))
(instance "OR4" (("cint_0n" 1) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "OR4" (("cint_0n" 0) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "OR4" (("fsum_0n" 3) ("mint_0n" 1) ("mint_0n" 6) ("mint_0n" 11) ("mint_0n" 12)))
(instance "OR4" (("fsum_0n" 2) ("mint_0n" 2) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 13)))
(instance "OR4" (("fsum_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 9) ("mint_0n" 14)))
(instance "OR4" (("fsum_0n" 0) ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 6)))
(instance "OR2" ("sum_3" "co_0" ("mint_0n" 6)))
(instance "OR2" ("sum_2" ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR2" ("sum_1" ("mint_0n" 2) ("mint_0n" 3)))
(instance "OR2" ("sum_0" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 4)
)
(instances
(instance "OR4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 3)))
(instance "OR2" ("sum_3" "co_0" ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_3" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
(instance "th23w2" ("sum_2" ("mint_0n" 2) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_2" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_1"))
(instance "th23w2" ("sum_0" ("mint_0n" 0) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "OR3" ("s_1" "sum_3" "sum_2" ("mint_0n" 3)))
(instance "OR2" ("s_0" "sum_0" ("mint_0n" 2)))
(instance "OR4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 6)))
(instance "OR2" ("sum_3" "co_0" ("mint_0n" 6)))
(instance "OR2" ("sum_2" ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR2" ("sum_1" ("mint_0n" 2) ("mint_0n" 3)))
(instance "OR2" ("sum_0" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 5)
)
(instances
(instance "OR3" ("s_1" "sum_3" "sum_2" ("mint_0n" 3)))
(instance "OR2" ("s_0" "sum_0" ("mint_0n" 2)))
(instance "OR4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 4)))
(instance "OR2" ("sum_3" "co_0" ("mint_0n" 4)))
(instance "c2" (("mint_0n" 4) "i0_3" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
(instance "OR2" ("sum_2" ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_2" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_1"))
(instance "th23w2" ("sum_0" ("mint_0n" 0) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 1)
)
(instances
(instance "OR4" ("co_1" ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("sopint_0n" 0) "sum_2" "sum_3"))
(instance "OR4" ("sum_3" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR4" ("sum_2" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "OR3" ("sum_1" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "OR3" ("sum_0" ("mint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 3)
("sumint_0n" 6)
("carint_0n" 5)
)
(instances
(instance "th23w2" ("co_1" ("carint_0n" 3) ("carint_0n" 4) "ci_1"))
(instance "OR3" (("carint_0n" 4) ("mint_0n" 0) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("carint_0n" 3) ("mint_0n" 0) "ci_0"))
(instance "OR3" ("co_0" ("carint_0n" 2) "sum_2" "sum_3"))
(instance "th23w2" (("carint_0n" 2) ("carint_0n" 1) ("carint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 1) ("carint_0n" 0) ("sopint_0n" 1) "ci_0"))
(instance "c2" (("carint_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 4) ("sumint_0n" 5) "ci_0"))
(instance "OR2" (("sumint_0n" 5) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("sumint_0n" 4) ("sopint_0n" 2) "ci_1"))
(instance "th23w2" ("sum_2" ("sumint_0n" 3) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sumint_0n" 2) "ci_1"))
(instance "OR2" (("sumint_0n" 2) ("sopint_0n" 0) ("mint_0n" 3)))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("mint_0n" 4) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 0) "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 2) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_3" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR2" ("s_1" ("sopint_0n" 2) ("mint_0n" 8)))
(instance "OR4" ("s_0" "sum_1" "sum_0" ("sopint_0n" 1) ("mint_0n" 7)))
(instance "OR4" ("co_1" ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("sopint_0n" 0) "sum_2" "sum_3"))
(instance "OR2" ("sum_3" ("mint_0n" 7) ("sopint_0n" 2)))
(instance "OR3" (("sopint_0n" 2) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR2" ("sum_2" ("sopint_0n" 1) ("mint_0n" 8)))
(instance "OR3" (("sopint_0n" 1) ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6)))
(instance "OR3" ("sum_1" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "OR3" ("sum_0" ("mint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 3)
("sumint_0n" 6)
("carint_0n" 5)
("exint_0n" 4)
)
(instances
(instance "th23w2" ("s_1" ("exint_0n" 3) ("mint_0n" 3) "ci_1"))
(instance "c2" (("exint_0n" 3) ("exint_0n" 2) "ci_0"))
(instance "OR3" (("exint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR3" ("s_0" "sum_1" "sum_0" ("exint_0n" 1)))
(instance "th23w2" (("exint_0n" 1) ("exint_0n" 0) ("mint_0n" 2) "ci_0"))
(instance "th23" (("exint_0n" 0) "ci_1" ("sopint_0n" 1) ("mint_0n" 2)))
(instance "th23w2" ("co_1" ("carint_0n" 3) ("carint_0n" 4) "ci_1"))
(instance "OR3" (("carint_0n" 4) ("mint_0n" 0) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("carint_0n" 3) ("mint_0n" 0) "ci_0"))
(instance "OR3" ("co_0" ("carint_0n" 2) "sum_2" "sum_3"))
(instance "th23w2" (("carint_0n" 2) ("carint_0n" 1) ("carint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 1) ("carint_0n" 0) ("sopint_0n" 1) "ci_0"))
(instance "c2" (("carint_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 4) ("sumint_0n" 5) "ci_0"))
(instance "OR2" (("sumint_0n" 5) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("sumint_0n" 4) ("sopint_0n" 2) "ci_1"))
(instance "th23w2" ("sum_2" ("sumint_0n" 3) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sumint_0n" 2) "ci_1"))
(instance "OR2" (("sumint_0n" 2) ("sopint_0n" 0) ("mint_0n" 4)))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("mint_0n" 5) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 0) "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "OR2" (("sopint_0n" 2) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_3" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 1)
)
(instances
(instance "OR3" ("co_1" ("sopint_0n" 0) "sum_0" "sum_1"))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "OR4" ("sum_3" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 15)))
(instance "OR4" ("sum_2" ("mint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" ("sum_1" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR4" ("sum_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 4)
("sumint_0n" 4)
("carint_0n" 2)
)
(instances
(instance "th23w2" ("co_1" ("carint_0n" 1) ("mint_0n" 1) "ci_0"))
(instance "th23" (("carint_0n" 1) ("sopint_0n" 3) ("mint_0n" 1) "ci_1"))
(instance "th23w2" ("co_0" ("carint_0n" 0) ("mint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 0) ("sopint_0n" 1) ("mint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_3" ("sumint_0n" 3) ("sopint_0n" 0) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_2" ("sumint_0n" 2) ("sopint_0n" 3) "ci_1"))
(instance "c2" (("sumint_0n" 2) ("sopint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sopint_0n" 2) "ci_1"))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 3) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 4) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "OR2" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("s_1" ("sopint_0n" 1) "sum_2" "sum_3"))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR4" ("s_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "OR3" ("co_1" ("sopint_0n" 0) "sum_0" "sum_1"))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "OR4" ("co_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "OR4" ("sum_3" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 15)))
(instance "OR4" ("sum_2" ("mint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" ("sum_1" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "OR4" ("sum_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 4)
("sumint_0n" 4)
("carint_0n" 2)
("exint_0n" 3)
)
(instances
(instance "OR3" ("s_1" "sum_2" "sum_3" ("exint_0n" 2)))
(instance "th23w2" (("exint_0n" 2) ("exint_0n" 1) ("mint_0n" 4) "ci_1"))
(instance "th23" (("exint_0n" 1) "ci_0" ("sopint_0n" 3) ("mint_0n" 4)))
(instance "th23w2" ("s_0" ("exint_0n" 0) ("mint_0n" 3) "ci_0"))
(instance "th23" (("exint_0n" 0) "ci_1" ("sopint_0n" 1) ("mint_0n" 3)))
(instance "th23w2" ("co_1" ("carint_0n" 1) ("mint_0n" 1) "ci_0"))
(instance "th23" (("carint_0n" 1) ("sopint_0n" 3) ("mint_0n" 1) "ci_1"))
(instance "th23w2" ("co_0" ("carint_0n" 0) ("mint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 0) ("sopint_0n" 1) ("mint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_3" ("sumint_0n" 3) ("sopint_0n" 0) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_2" ("sumint_0n" 2) ("sopint_0n" 3) "ci_1"))
(instance "c2" (("sumint_0n" 2) ("sopint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sopint_0n" 2) "ci_1"))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 3) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "OR2" (("sopint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "OR2" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 15)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("q0_2" ("mint_0n" 10) ("mint_0n" 11) ("mint_0n" 14)))
(instance "OR3" ("q0_1" ("mint_0n" 5) ("mint_0n" 7) ("mint_0n" 13)))
(instance "OR3" ("q0_0" ("mint_0n" 12) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 4) ("mint_0n" 6) ("mint_0n" 8) ("mint_0n" 9)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" ("q0_3" "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_3" "i0_3" "i1_3"))
(instance "th23w2" ("q0_2" ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23" (("mint_0n" 5) "i0_2" "i1_2" "i1_3"))
(instance "th23w2" ("q0_1" ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23" (("mint_0n" 4) "i0_1" "i1_1" "i1_3"))
(instance "th23w2" ("q0_0" ("sopint_0n" 0) "i0_3" "i1_0"))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_1" "i1_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_0" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 15)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("q0_3" ("mint_0n" 14) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 10) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "OR3" ("q0_2" ("mint_0n" 1) ("mint_0n" 7) ("mint_0n" 9)))
(instance "OR3" ("q0_1" ("mint_0n" 0) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 11) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 7) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
(instance "c2" ("q0_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_3" ("sopint_0n" 0) "i0_0" "i1_3"))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "th23" (("mint_0n" 5) "i0_3" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 4) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_1" "i1_3"))
(instance "th23" (("mint_0n" 2) "i0_1" "i1_2" "i1_3"))
(instance "th23w2" ("q0_2" ("mint_0n" 1) "i0_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_2"))
(instance "th23w2" ("q0_1" ("mint_0n" 0) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
(instance "c2" ("q0_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 16)
)
(instances
(instance "OR4" ("q0_3" ("mint_0n" 3) ("mint_0n" 6) ("mint_0n" 9) ("mint_0n" 12)))
(instance "OR4" ("q0_2" ("mint_0n" 2) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 13)))
(instance "OR4" ("q0_1" ("mint_0n" 1) ("mint_0n" 4) ("mint_0n" 11) ("mint_0n" 14)))
(instance "OR4" ("q0_0" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 8)
)
(instances
(instance "OR2" ("q0_3" ("sopint_0n" 6) ("sopint_0n" 7)))
(instance "th23w2" (("sopint_0n" 7) ("mint_0n" 7) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_2"))
(instance "th23w2" (("sopint_0n" 6) ("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 6) "i0_0" "i1_3"))
(instance "OR2" ("q0_2" ("sopint_0n" 4) ("sopint_0n" 5)))
(instance "th23w2" (("sopint_0n" 5) ("mint_0n" 5) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_3"))
(instance "th23w2" (("sopint_0n" 4) ("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_2"))
(instance "OR2" ("q0_1" ("sopint_0n" 2) ("sopint_0n" 3)))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 3) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_3"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "OR2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR4" ("q0_1" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "OR3" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "OR4" (("sopint_0n" 2) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 9)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 2)
)
(instances
(instance "OR2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 5) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 4) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_0"))
(instance "OR4" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th34w2" (("mint_0n" 3) "i0_3" "i1_1" "i1_1" "i1_2"))
(instance "th34w2" (("mint_0n" 2) "i0_2" "i1_0" "i1_1" "i1_3"))
(instance "th34w2" (("mint_0n" 1) "i0_1" "i1_0" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 0) "i0_0" "i1_1" "i1_2" "i1_3"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 0) ("mint_0n" 3)))
(instance "OR3" ("q0_0" ("mint_0n" 1) ("mint_0n" 2) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_1" ("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_0"))
(instance "OR2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_2" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR3" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "OR4" (("sopint_0n" 2) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 9)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "OR4" ("q0_0" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 2)
)
(instances
(instance "OR4" ("q0_1" ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "th34w2" (("mint_0n" 5) "i0_3" "i1_1" "i1_1" "i1_2"))
(instance "th34w2" (("mint_0n" 4) "i0_2" "i1_0" "i1_1" "i1_3"))
(instance "th34w2" (("mint_0n" 3) "i0_1" "i1_0" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 2) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "OR2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR3" ("q0_1" ("mint_0n" 1) ("mint_0n" 2) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "OR2" ("q0_0" ("mint_0n" 0) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 2)
)
(instances
(instance "OR2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("q0_2" ("sopint_0n" 1) ("mint_0n" 7) ("mint_0n" 11)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "OR4" ("q0_1" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "OR3" ("q0_0" ("sopint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "OR3" ("q0_2" ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 6) "i0_1" "i1_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "OR2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 4) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_0"))
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th34w2" (("mint_0n" 2) "i0_3" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 0) ("mint_0n" 2)))
(instance "OR2" ("q0_0" ("mint_0n" 6) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_0"))
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ineq_sgn_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 0) ("mint_0n" 2)))
(instance "OR2" ("q0_2" ("mint_0n" 6) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ineq_sgn_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "OR3" ("q0_2" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th23" (("mint_0n" 3) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR3" ("q0_1" ("sopint_0n" 2) ("mint_0n" 7) ("mint_0n" 11)))
(instance "OR4" (("sopint_0n" 2) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "OR4" ("q0_0" ("mint_0n" 14) ("mint_0n" 15) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12) ("mint_0n" 13)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 8)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR3" (("q0__1_0n" 0) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 6) "i0_1" "i1_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "OR3" ("q0_0" ("mint_0n" 3) ("mint_0n" 4) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 4) "i0_3" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 3) "i0_3" "i1_0" "i1_1"))
(instance "th34w2" (("mint_0n" 2) "i0_2" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_1" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "OR3" ("q0_1" ("sopint_0n" 2) ("mint_0n" 13) ("mint_0n" 14)))
(instance "OR4" (("sopint_0n" 2) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "OR4" ("q0_0" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "OR4" (("sopint_0n" 1) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 10)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR3" ("q0_1" ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_3" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 6) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_0"))
(instance "OR3" ("q0_0" ("mint_0n" 3) ("mint_0n" 4) ("sopint_0n" 0)))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 4) "i0_3" "i1_3"))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 2) "i0_1" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 1) "i0_0" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "OR4" ("q0_0" ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "th23w2" ("q0_0" ("sopint_0n" 0) "i0_0" "i1_0"))
(instance "OR3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 7) ("sopint_0n" 0)))
(instance "OR4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6)))
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_1" ("sopint_0n" 0) "i0_1" "i1_0"))
(instance "OR2" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "OR2" ("q0_1" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
)
(instances
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_0" "i1_0"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" ("q0_1" "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_1" "i1_0"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_oot_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
)
(instances
(instance "OR3" ("q0_1" ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "OR3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_oot_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q0_1" ("mint_0n" 1) "i0_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_1" "i1_1" "i1_2"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_0"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oot_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 9)
)
(instances
(instance "OR4" ("q0_2" ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "OR4" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 6) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_2"))
(instance "c2" ("q0_1" "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oot_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q0_2" ("mint_0n" 1) "i0_1" "i1_2"))
(instance "th34w2" (("mint_0n" 1) "i0_2" "i1_0" "i1_1" "i1_2"))
(instance "c2" ("q0_1" "i0_1" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_0"))
(instance "th34w2" (("mint_0n" 0) "i0_0" "i1_0" "i1_1" "i1_2"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
)
(instances
(instance "ao22" ("in_a" "in_0" "out_0" "in_1" "out_1"))
(instance "NOR2" ("out_0" "in_1" "out_1"))
(instance "NOR2" ("out_1" "in_0" "out_0"))
)
(attributes (simulation-initialise ("out_0" 1)) (cell-type "helper"))
)
(circuit "dr_spacer_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("phaseOne_0n" 2)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "OR2" ("in_a" ("phaseOne_0n" 0) ("phaseOne_0n" 1)))
(instance "OR2" (("outcomp_0n" 0) "out_0" "out_1"))
(instance "OR2" (("incomp_0n" 0) "in_0" "in_1"))
(instance "NOR3" ("out_1" ("incomp_0n" 0) ("phaseOne_0n" 1) "out_0"))
(instance "NOR3" ("out_0" ("incomp_0n" 0) ("phaseOne_0n" 0) "out_1"))
(instance "NOR3" (("phaseOne_0n" 1) ("outcomp_0n" 0) "in_1" ("phaseOne_0n" 0)))
(instance "NOR3" (("phaseOne_0n" 0) ("outcomp_0n" 0) "in_0" ("phaseOne_0n" 1)))
)
(attributes (simulation-initialise ("out_0" 1)) (cell-type "helper"))
)
(circuit "dr_ncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("phaseOne_0n" 2)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "OR2" ("in_a" ("phaseOne_0n" 0) ("phaseOne_0n" 1)))
(instance "NOR2" (("outcomp_0n" 0) "out_0" "out_1"))
(instance "NOR2" (("incomp_0n" 0) "in_0" "in_1"))
(instance "c2" ("out_1" ("phaseOne_0n" 1) ("incomp_0n" 0)))
(instance "c2" ("out_0" ("phaseOne_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("phaseOne_0n" 1) "in_1" ("outcomp_0n" 0)))
(instance "c2" (("phaseOne_0n" 0) "in_0" ("outcomp_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_tncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_r" input 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("writeSel_0n" 2)
("phaseOne_0n" 2)
("phaseTwo_0n" 2)
("readStore_0n" 2)
("wrcomp_0n" 1)
("incomp_0n" 1)
("pocomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "c2" ("in_a" ("pocomp_0n" 0) ("wrcomp_0n" 0)))
(instance "OR2" (("pocomp_0n" 0) ("phaseOne_0n" 0) ("phaseOne_0n" 1)))
(instance "NOR2" (("outcomp_0n" 0) ("phaseTwo_0n" 0) ("phaseTwo_0n" 1)))
(instance "NOR2" (("incomp_0n" 0) ("writeSel_0n" 0) ("writeSel_0n" 1)))
(instance "OR2" (("wrcomp_0n" 0) "in_0" "in_1"))
(instance "c2" ("out_1" ("readStore_0n" 1) ("pocomp_0n" 0)))
(instance "c2" ("out_0" ("readStore_0n" 0) ("pocomp_0n" 0)))
(instance "c2" (("readStore_0n" 1) ("phaseTwo_0n" 1) "out_r"))
(instance "c2" (("readStore_0n" 0) ("phaseTwo_0n" 0) "out_r"))
(instance "c2" (("phaseTwo_0n" 1) ("phaseOne_0n" 1) ("incomp_0n" 0)))
(instance "c2" (("phaseTwo_0n" 0) ("phaseOne_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("phaseOne_0n" 1) ("writeSel_0n" 1) ("outcomp_0n" 0)))
(instance "c2" (("phaseOne_0n" 0) ("writeSel_0n" 0) ("outcomp_0n" 0)))
(instance "OR2" (("writeSel_0n" 1) "in_1" ("readStore_0n" 1)))
(instance "OR2" (("writeSel_0n" 0) "in_0" ("readStore_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("inp__nor_0n" 4)
("cross__na_0n" 2)
("nor__latch_0n" 4)
("group__na_0n" 4)
("ack__na_0n" 2)
("ph__4_0n" 4)
)
(instances
(instance "OR2" ("in_a" ("ack__na_0n" 0) ("ack__na_0n" 1)))
(instance "NAND2" (("ack__na_0n" 1) ("group__na_0n" 2) ("group__na_0n" 3)))
(instance "NAND2" (("ack__na_0n" 0) ("group__na_0n" 0) ("group__na_0n" 1)))
(instance "NAND2" (("group__na_0n" 3) "in_3" ("nor__latch_0n" 3)))
(instance "NAND2" (("group__na_0n" 2) "in_2" ("nor__latch_0n" 2)))
(instance "NAND2" (("group__na_0n" 1) "in_1" ("nor__latch_0n" 1)))
(instance "NAND2" (("group__na_0n" 0) "in_0" ("nor__latch_0n" 0)))
(instance "NOR2" (("nor__latch_0n" 3) ("cross__na_0n" 0) "out_2"))
(instance "NOR2" (("nor__latch_0n" 2) ("cross__na_0n" 0) "out_3"))
(instance "NOR2" (("nor__latch_0n" 1) ("cross__na_0n" 1) "out_0"))
(instance "NOR2" (("nor__latch_0n" 0) ("cross__na_0n" 1) "out_1"))
(instance "NAND2" (("cross__na_0n" 1) ("inp__nor_0n" 2) ("inp__nor_0n" 3)))
(instance "NAND2" (("cross__na_0n" 0) ("inp__nor_0n" 0) ("inp__nor_0n" 1)))
(instance "INV" ("out_3" ("inp__nor_0n" 3)))
(instance "INV" ("out_2" ("inp__nor_0n" 2)))
(instance "INV" ("out_1" ("inp__nor_0n" 1)))
(instance "INV" ("out_0" ("inp__nor_0n" 0)))
(instance "NOR2" (("inp__nor_0n" 3) "in_3" ("nor__latch_0n" 3)))
(instance "NOR2" (("inp__nor_0n" 2) "in_2" ("nor__latch_0n" 2)))
(instance "NOR2" (("inp__nor_0n" 1) "in_1" ("nor__latch_0n" 1)))
(instance "NOR2" (("inp__nor_0n" 0) "in_0" ("nor__latch_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("PhaseOne_0n" 4)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "OR4" ("in_a" ("PhaseOne_0n" 0) ("PhaseOne_0n" 1) ("PhaseOne_0n" 2) ("PhaseOne_0n" 3)))
(instance "NOR4" (("outcomp_0n" 0) "out_0" "out_1" "out_2" "out_3"))
(instance "NOR4" (("incomp_0n" 0) "in_0" "in_1" "in_2" "in_3"))
(instance "c2" ("out_3" ("PhaseOne_0n" 3) ("incomp_0n" 0)))
(instance "c2" ("out_2" ("PhaseOne_0n" 2) ("incomp_0n" 0)))
(instance "c2" ("out_1" ("PhaseOne_0n" 1) ("incomp_0n" 0)))
(instance "c2" ("out_0" ("PhaseOne_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 3) "in_3" ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 2) "in_2" ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 1) "in_1" ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 0) "in_0" ("outcomp_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_tncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_r" input 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("WriteSel_0n" 4)
("PhaseOne_0n" 4)
("PhaseTwo_0n" 4)
("ReadStore_0n" 4)
("wrcomp_0n" 1)
("incomp_0n" 1)
("pocomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "c2" ("in_a" ("pocomp_0n" 0) ("wrcomp_0n" 0)))
(instance "OR4" (("pocomp_0n" 0) ("PhaseOne_0n" 0) ("PhaseOne_0n" 1) ("PhaseOne_0n" 2) ("PhaseOne_0n" 3)))
(instance "NOR4" (("outcomp_0n" 0) ("PhaseTwo_0n" 0) ("PhaseTwo_0n" 1) ("PhaseTwo_0n" 2) ("PhaseTwo_0n" 3)))
(instance "NOR4" (("incomp_0n" 0) ("WriteSel_0n" 0) ("WriteSel_0n" 1) ("WriteSel_0n" 2) ("WriteSel_0n" 3)))
(instance "OR4" (("wrcomp_0n" 0) "in_0" "in_1" "in_2" "in_3"))
(instance "c2" ("out_3" ("ReadStore_0n" 3) ("pocomp_0n" 0)))
(instance "c2" ("out_2" ("ReadStore_0n" 2) ("pocomp_0n" 0)))
(instance "c2" ("out_1" ("ReadStore_0n" 1) ("pocomp_0n" 0)))
(instance "c2" ("out_0" ("ReadStore_0n" 0) ("pocomp_0n" 0)))
(instance "c2" (("ReadStore_0n" 3) ("PhaseTwo_0n" 3) "out_r"))
(instance "c2" (("ReadStore_0n" 2) ("PhaseTwo_0n" 2) "out_r"))
(instance "c2" (("ReadStore_0n" 1) ("PhaseTwo_0n" 1) "out_r"))
(instance "c2" (("ReadStore_0n" 0) ("PhaseTwo_0n" 0) "out_r"))
(instance "c2" (("PhaseTwo_0n" 3) ("PhaseOne_0n" 3) ("incomp_0n" 0)))
(instance "c2" (("PhaseTwo_0n" 2) ("PhaseOne_0n" 2) ("incomp_0n" 0)))
(instance "c2" (("PhaseTwo_0n" 1) ("PhaseOne_0n" 1) ("incomp_0n" 0)))
(instance "c2" (("PhaseTwo_0n" 0) ("PhaseOne_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 3) ("WriteSel_0n" 3) ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 2) ("WriteSel_0n" 2) ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 1) ("WriteSel_0n" 1) ("outcomp_0n" 0)))
(instance "c2" (("PhaseOne_0n" 0) ("WriteSel_0n" 0) ("outcomp_0n" 0)))
(instance "OR2" (("WriteSel_0n" 3) "in_3" ("ReadStore_0n" 3)))
(instance "OR2" (("WriteSel_0n" 2) "in_2" ("ReadStore_0n" 2)))
(instance "OR2" (("WriteSel_0n" 1) "in_1" ("ReadStore_0n" 1)))
(instance "OR2" (("WriteSel_0n" 0) "in_0" ("ReadStore_0n" 0)))
)
(attributes (cell-type "helper"))
)
balsa-tech-xilinx/xilinx/.svn/text-base/drive-table.svn-base0000444003172000014400000000000010212061546024257 0ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/prop-base/0000755003172000014400000000000010212061546020431 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/prop-base/gate-mappings.svn-base0000444003172000014400000000000410212061546024615 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/Makefile.am.svn-base0000444003172000014400000000000410212061546024172 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/components.abs.svn-base0000444003172000014400000000000410212061546025012 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/balsa-mgr.cfg.svn-base0000444003172000014400000000000410212061546024464 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/gate-mappings-caps.svn-base0000444003172000014400000000000410212061546025541 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/xilinx.svn-base0000444003172000014400000000000410212061546023374 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/xilinx-cells.net.svn-base0000444003172000014400000000000410212061546025261 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/xilinx-cells-caps.net.svn-base0000444003172000014400000000000410212061546026205 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/balsa-cells.net.svn-base0000444003172000014400000000000410212061546025030 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/balsa-cells-caps.net.svn-base0000444003172000014400000000000410212061546025754 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/prop-base/drive-table.svn-base0000444003172000014400000000000410212061546024257 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/0000755003172000014400000000000010212061546017704 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/props/components.abs.svn-work0000444003172000014400000000000410212061546024335 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/gate-mappings.svn-work0000444003172000014400000000000410212061546024140 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/drive-table.svn-work0000444003172000014400000000000410212061546023602 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/xilinx-cells-caps.net.svn-work0000444003172000014400000000000410212061546025530 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/gate-mappings-caps.svn-work0000444003172000014400000000000410212061546025064 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/xilinx.svn-work0000444003172000014400000000000410212061546022717 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/Makefile.am.svn-work0000444003172000014400000000000410212061546023515 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/balsa-mgr.cfg.svn-work0000444003172000014400000000000410212061546024007 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/balsa-cells-caps.net.svn-work0000444003172000014400000000000410212061546025277 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/balsa-cells.net.svn-work0000444003172000014400000000000410212061546024353 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/props/xilinx-cells.net.svn-work0000444003172000014400000000000410212061546024604 0ustar tomswapt00000000000000END
balsa-tech-xilinx/xilinx/.svn/format0000444003172000014400000000000210212061546017742 0ustar tomswapt000000000000004
balsa-tech-xilinx/xilinx/.svn/tmp/0000755003172000014400000000000010212061546017341 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/tmp/text-base/0000755003172000014400000000000010212061546021235 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/tmp/prop-base/0000755003172000014400000000000010212061546021231 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/tmp/props/0000755003172000014400000000000010212061546020504 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/tmp/wcprops/0000755003172000014400000000000010212061546021036 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/entries0000444003172000014400000000651310212061546020140 0ustar tomswapt00000000000000
balsa-tech-xilinx/xilinx/.svn/empty-file0000444003172000014400000000000010212061546020523 0ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/.svn/README.txt0000444003172000014400000000016610212061546020240 0ustar tomswapt00000000000000This is a Subversion working copy administrative directory.
Visit http://subversion.tigris.org/ for more information.
balsa-tech-xilinx/xilinx/.svn/wcprops/0000755003172000014400000000000010212061546020236 5ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/balsa-mgr.cfg0000644003172000014400000000407310212061546020207 0ustar tomswapt00000000000000(balsa-mgr-technology "xilinx"
(description "Generic Xilinx technology")
(balsa-netlist-options "-f -i helper")
(style-options
(style-option "sim"
(enumeration
("icarus" "Icarus Verilog")
("vxl" "Cadence Verilog-XL")
("ncv" "Cadence NC-Verilog")
("vcs" "Synonsys VCS")
("modelsim" "Modelsim")
("cver" "Cver")
)
"Simulator to use for implementation simulation"
)
(style-option "suggest-buffers"
(boolean)
"Add defaults buffers in suggested drive-up buffer insertion points"
)
(style-option "cad"
(enumeration
("ise" "Xilinx ISE tools")
("cadence" "Cadence Xilinx Design Flow")
)
"Target CAD tool"
)
)
(styles
(style "four_b_rb"
(description "Bundled data, single-rail, 4-phase broad/reduced-broad")
(allowed-style-options "sim" "suggest-buffers" "cad")
)
(style "dual_b"
(style-options
(style-option "logic"
(enumeration
("dims" "DIMS logic implementations")
("ncl" "NCL gates")
("balanced" (boolean) "`Balanced' logic")
)
"Style of dual-rail logic"
)
(style-option "variable"
(enumeration
("sr" "Set-rest flip-flops")
("spacer" "Reset-before-set variables")
("ncl" "NCL pipeline latch")
)
"Style of dual-rail variables"
)
(style-option "n-of-m-mapping" (boolean) "Unoptimised DIMS enc/decoders")
)
(description "Dual-rail with broad sync channels")
(allowed-style-options "sim" "suggest-buffers" "logic" "variable" "n-of-m-mapping" "cad")
)
(style "one_of_2_4"
(style-options
(style-option "logic"
(enumeration
("dims" "DIMS logic implementations")
("ncl" "NCL gates")
)
"Style of 1-of-4 logic"
)
(style-option "variable"
(enumeration
("sr" "Set-rest flip-flops")
("ncl" "NCL pipeline latch")
)
"Style of 1-of-4 variables"
)
(style-option "n-of-m-mapping" (boolean) "Unoptimised DIMS enc/decoders")
)
(description "1-of-4 with dual rail `odd' bits")
(allowed-style-options "sim" "suggest-buffers" "logic" "variable" "cad")
)
)
)
balsa-tech-xilinx/xilinx/balsa-cells.net0000644003172000014400000042541310212067630020560 0ustar tomswapt00000000000000;;; `helper-cells'
;;; xilinx Balsa helper cells
;;; Created: Mon Mar 8 15:50:44 GMT 2004
;;; By: Sam Taylor (Linux)
;;; With net-net version: 20031009
(circuit "mutex1"
(ports
("q0" output 1)
("q1" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "nand2" (("int_0n" 0) "i0" ("int_0n" 1)))
(instance "nand2" (("int_0n" 1) "i1" ("int_0n" 0)))
(instance "nor3" ("q0" ("int_0n" 0) ("int_0n" 0) ("int_0n" 0)))
(instance "nor3" ("q1" ("int_0n" 1) ("int_0n" 1) ("int_0n" 1)))
)
(attributes (cell-type "helper"))
)
(circuit "ao22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "or2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "and2" (("int_0n" 1) "i2" "i3"))
(instance "and2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "aoi22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("int_0n" 2)
)
(instances
(instance "nor2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "and2" (("int_0n" 1) "i2" "i3"))
(instance "and2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "ao222"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
("i4" input 1)
("i5" input 1)
)
(nets
("int_0n" 3)
)
(instances
(instance "or3" ("q" ("int_0n" 0) ("int_0n" 1) ("int_0n" 2)))
(instance "and2" (("int_0n" 2) "i4" "i5"))
(instance "and2" (("int_0n" 1) "i2" "i3"))
(instance "and2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "aoi222"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
("i4" input 1)
("i5" input 1)
)
(nets
("int_0n" 3)
)
(instances
(instance "nor3" ("q" ("int_0n" 0) ("int_0n" 1) ("int_0n" 2)))
(instance "and2" (("int_0n" 2) "i4" "i5"))
(instance "and2" (("int_0n" 1) "i2" "i3"))
(instance "and2" (("int_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "srff"
(ports
("s" input 1)
("r" input 1)
("q" output 1)
("nq" output 1)
)
(nets
)
(instances
(instance "nor2" ("nq" "q" "s"))
(instance "nor2" ("q" "nq" "r"))
)
(attributes (simulation-initialise ("q" 0)) (cell-type "helper"))
)
(circuit "mux2"
(ports
("q" output 1)
("d0" input 1)
("d1" input 1)
("sel" input 1)
)
(nets
("int_0n" 2)
("nsel_0n" 1)
)
(instances
(instance "nand2" ("q" ("int_0n" 0) ("int_0n" 1)))
(instance "nand2" (("int_0n" 1) "d1" "sel"))
(instance "nand2" (("int_0n" 0) "d0" ("nsel_0n" 0)))
(instance "inv" (("nsel_0n" 0) "sel"))
)
(attributes (cell-type "helper"))
)
(circuit "nmux2"
(ports
("q" output 1)
("d0" input 1)
("d1" input 1)
("sel" input 1)
)
(nets
("int_0n" 2)
("nsel_0n" 1)
("nq_0n" 1)
)
(instances
(instance "inv" ("q" ("nq_0n" 0)))
(instance "nand2" (("nq_0n" 0) ("int_0n" 0) ("int_0n" 1)))
(instance "nand2" (("int_0n" 1) "d1" "sel"))
(instance "nand2" (("int_0n" 0) "d0" ("nsel_0n" 0)))
(instance "inv" (("nsel_0n" 0) "sel"))
)
(attributes (cell-type "helper"))
)
(circuit "balsa_fa"
(ports
("nStart" input 1)
("A" input 1)
("B" input 1)
("nCVi" input 1)
("Ci" input 1)
("nCVo" output 1)
("Co" output 1)
("sum" output 1)
)
(nets
("start_0n" 1)
("ha_0n" 1)
("cv_0n" 1)
)
(instances
(instance "xor2" ("sum" ("ha_0n" 0) "Ci"))
(instance "xor2" (("ha_0n" 0) "A" "B"))
(instance "mux2" ("Co" "A" "Ci" ("ha_0n" 0)))
(instance "nmux2" ("nCVo" ("start_0n" 0) ("cv_0n" 0) ("ha_0n" 0)))
(instance "nor2" (("cv_0n" 0) "nStart" "nCVi"))
(instance "inv" (("start_0n" 0) "nStart"))
)
(attributes (cell-type "helper"))
)
(circuit "c2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
)
(instances
(instance "ao222" ("q" "i0" "i1" "i0" "q" "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "c3"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("qint_0n" 1)
)
(instances
(instance "c2" ("q" "i2" ("qint_0n" 0)))
(instance "c2" (("qint_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "nc2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("nq_0n" 1)
)
(instances
(instance "aoi222" ("q" "i0" "i1" "i0" ("nq_0n" 0) "i1" ("nq_0n" 0)))
(instance "inv" (("nq_0n" 0) "q"))
)
(attributes (cell-type "helper"))
)
(circuit "nc2p"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("nq_0n" 1)
)
(instances
(instance "aoi22" ("q" "i0" "i1" "i0" ("nq_0n" 0)))
(instance "inv" (("nq_0n" 0) "q"))
)
(attributes (cell-type "helper"))
)
(circuit "demux2"
(ports
("i" input 1)
("o0" output 1)
("o1" output 1)
("s" input 1)
)
(nets
("ns_0n" 1)
)
(instances
(instance "and2" ("o1" "i" "s"))
(instance "and2" ("o0" "i" ("ns_0n" 0)))
(instance "inv" (("ns_0n" 0) "s"))
)
(attributes (cell-type "helper"))
)
(circuit "selem"
(ports
("Ar" input 1)
("Aa" output 1)
("Br" output 1)
("Ba" input 1)
)
(nets
("s_0n" 1)
)
(instances
(instance "nc2p" (("s_0n" 0) "Ar" "Ba"))
(instance "nor2" ("Aa" "Ba" ("s_0n" 0)))
(instance "and2" ("Br" "Ar" ("s_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "th22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
)
(nets
("qint_0n" 3)
)
(instances
(instance "or3" ("q" ("qint_0n" 0) ("qint_0n" 1) ("qint_0n" 2)))
(instance "and2" (("qint_0n" 2) "i1" "q"))
(instance "and2" (("qint_0n" 1) "i0" "q"))
(instance "and2" (("qint_0n" 0) "i0" "i1"))
)
(attributes (cell-type "helper"))
)
(circuit "th33"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("qint_0n" 2)
)
(instances
(instance "or2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "or3" (("qint_0n" 1) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "and2" (("qint_0n" 0) "i1" "i2"))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th23"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 2)
("qint_0n" 2)
("sinti_0n" 1)
)
(instances
(instance "or2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "or2" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1)))
(instance "and2" (("sint_0n" 1) "i0" ("sinti_0n" 0)))
(instance "and2" (("sint_0n" 0) "i1" "i2"))
(instance "or2" (("sinti_0n" 0) "i1" "i2"))
(instance "or3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th23w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 2)
("sint_0n" 1)
)
(instances
(instance "or4" ("q" "i0" ("hint_0n" 0) ("hint_0n" 1) ("sint_0n" 0)))
(instance "and2" (("sint_0n" 0) "i1" "i2"))
(instance "and2" (("hint_0n" 1) "i2" "q"))
(instance "and2" (("hint_0n" 0) "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 4)
("sint_0n" 6)
("qint_0n" 3)
)
(instances
(instance "or3" ("q" ("qint_0n" 0) ("qint_0n" 1) ("qint_0n" 2)))
(instance "or3" (("qint_0n" 2) ("sint_0n" 3) ("sint_0n" 4) ("sint_0n" 5)))
(instance "or3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "and2" (("sint_0n" 5) "i2" "i3"))
(instance "and2" (("sint_0n" 4) "i1" "i3"))
(instance "and2" (("sint_0n" 3) "i1" "i2"))
(instance "and2" (("sint_0n" 2) "i0" "i3"))
(instance "and2" (("sint_0n" 1) "i0" "i2"))
(instance "and2" (("sint_0n" 0) "i0" "i1"))
(instance "or4" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2) ("hint_0n" 3)))
(instance "and2" (("hint_0n" 3) "i3" "q"))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 3)
("qint_0n" 2)
)
(instances
(instance "or3" ("q" ("qint_0n" 0) ("qint_0n" 1) "i0"))
(instance "or3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "and2" (("sint_0n" 2) "i2" "i3"))
(instance "and2" (("sint_0n" 1) "i1" "i3"))
(instance "and2" (("sint_0n" 0) "i1" "i2"))
(instance "or3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "and2" (("hint_0n" 2) "i3" "q"))
(instance "and2" (("hint_0n" 1) "i2" "q"))
(instance "and2" (("hint_0n" 0) "i1" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th24w22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 2)
("sint_0n" 1)
("qint_0n" 1)
)
(instances
(instance "or3" ("q" "i0" "i1" ("qint_0n" 0)))
(instance "or3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("sint_0n" 0)))
(instance "and2" (("sint_0n" 0) "i2" "i3"))
(instance "and2" (("hint_0n" 1) "i3" "q"))
(instance "and2" (("hint_0n" 0) "i2" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th33w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
)
(nets
("hint_0n" 3)
("sint_0n" 1)
("qint_0n" 2)
)
(instances
(instance "or2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "or3" (("qint_0n" 2) ("sint_0n" 3) ("sint_0n" 4) ("sint_0n" 5)))
(instance "or3" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1) ("sint_0n" 2)))
(instance "and2" (("qint_0n" 1) "i0" ("sint_0n" 0)))
(instance "or2" (("sint_0n" 0) "i1" "i2"))
(instance "or3" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2)))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th34"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("hint_0n" 4)
("sint_0n" 2)
("qint_0n" 2)
("sinti_0n" 2)
)
(instances
(instance "or2" ("q" ("qint_0n" 0) ("qint_0n" 1)))
(instance "or2" (("qint_0n" 1) ("sint_0n" 0) ("sint_0n" 1)))
(instance "and3" (("sint_0n" 1) "i1" "i3" ("sinti_0n" 1)))
(instance "or2" (("sinti_0n" 1) "i0" "i2"))
(instance "and3" (("sint_0n" 0) "i0" "i2" ("sinti_0n" 0)))
(instance "or2" (("sinti_0n" 0) "i1" "i3"))
(instance "or4" (("qint_0n" 0) ("hint_0n" 0) ("hint_0n" 1) ("hint_0n" 2) ("hint_0n" 3)))
(instance "and2" (("hint_0n" 3) "i3" "q"))
(instance "and2" (("hint_0n" 2) "i2" "q"))
(instance "and2" (("hint_0n" 1) "i1" "q"))
(instance "and2" (("hint_0n" 0) "i0" "q"))
)
(attributes (cell-type "helper"))
)
(circuit "th34w2"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q" ("mint_0n" 0) ("mint_0n" 1) "i0"))
(instance "or3" (("mint_0n" 1) "i1" "i2" "i3"))
(instance "c3" (("mint_0n" 0) "i1" "i2" "i3"))
)
(attributes (cell-type "helper"))
)
(circuit "th34w22"
(ports
("q" output 1)
("i0" input 1)
("i1" input 1)
("i2" input 1)
("i3" input 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "th23" ("q" ("mint_0n" 0) "i0" "i1"))
(instance "or2" (("mint_0n" 0) "i2" "i3"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "or3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
(instance "c2" ("q_1" "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
(instance "or3" ("q_1" "gnd" ("n3_0n" 0) "gnd"))
(instance "c2" (("n3_0n" 0) "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_and2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "c2" ("q_1" "i0_1" "i1_1"))
(instance "th34w22" ("q_0" "i0_0" "i1_0" "i0_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "c2" ("q_0" "i0_0" "i1_0"))
(instance "or3" ("q_1" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("q_0" "gnd" ("n3_0n" 0) "gnd"))
(instance "c2" (("n3_0n" 0) "i0_0" "i1_0"))
(instance "or3" ("q_1" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_or2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "th34w22" ("q_1" "i0_1" "i1_1" "i0_0" "i1_0"))
(instance "c2" ("q_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_nor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "c2" ("q_1" "i0_0" "i1_0"))
(instance "or3" ("q_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_nor2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
)
(instances
(instance "c2" ("q_1" "i0_0" "i1_0"))
(instance "th34w22" ("q_0" "i0_1" "i1_1" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or2" ("q_0" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
(instance "or2" ("q_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "c2" (("n2_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_xor2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "th23w2" ("q_1" ("n1_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("n1_0n" 0) "i0_0" "i1_1"))
(instance "th23w2" ("q_0" ("n0_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("n0_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2_bal" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2_bal" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ao21_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "dr_or2_ncl" (("n0_0n" 0) ("n1_0n" 0) "i2_0" "i2_1" "q_0" "q_1"))
(instance "dr_and2_ncl" ("i0_0" "i0_1" "i1_0" "i1_1" ("n0_0n" 0) ("n1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp_bal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21_bal" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2_bal" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ineq_comp_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i2_0" input 1)
("i2_1" input 1)
("i3_0" input 1)
("i3_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
)
(instances
(instance "dr_ao21_ncl" ("i2_0" "i2_1" "i1_0" "i1_1" "i0_0" "i0_1" "q0_0" "q0_1"))
(instance "dr_and2_ncl" ("i1_0" "i1_1" "i3_0" "i3_1" "q1_0" "q1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_mux2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("s_0" input 1)
("s_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or2" ("q_0" ("n0_0n" 0) ("n2_0n" 0)))
(instance "c2" (("n0_0n" 0) "s_0" "i0_0"))
(instance "c2" (("n2_0n" 0) "s_1" "i1_0"))
(instance "or2" ("q_1" ("n1_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n1_0n" 0) "s_0" "i0_1"))
(instance "c2" (("n3_0n" 0) "s_1" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_mux2_ncl"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("s_0" input 1)
("s_1" input 1)
("q_0" output 1)
("q_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
)
(instances
(instance "th23w2" ("q_1" ("n1_0n" 0) "s_0" "i0_1"))
(instance "c2" (("n1_0n" 0) "s_1" "i1_1"))
(instance "th23w2" ("q_0" ("n0_0n" 0) "s_0" "i0_0"))
(instance "c2" (("n0_0n" 0) "s_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
)
(instances
(instance "or3" ("co_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_0" ("n0_0n" 0) "co_1"))
(instance "c2" ("co_1" "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("co_1" "gnd" ("n3_0n" 0) "gnd"))
(instance "or3" ("co_0" ("n0_0n" 0) ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_1" ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_0" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ha_ncl"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
)
(instances
(instance "th23w2" ("co_0" "sum_1" "a_0" "b_0"))
(instance "th23w2" ("sum_1" ("n0_0n" 0) "a_1" "b_0"))
(instance "c2" (("n0_0n" 0) "a_0" "b_1"))
(instance "th23w2" ("sum_0" "co_1" "a_0" "b_0"))
(instance "c2" ("co_1" "a_1" "b_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("ha__1_0n" 1)
("ha__0_0n" 1)
("n0__1_0n" 1)
("n0_0n" 1)
)
(instances
(instance "th23w2" ("co_0" "sum_1" "a_0" "b_0"))
(instance "th23w2" ("sum_1" ("n0_0n" 0) "a_1" "b_0"))
(instance "c2" (("n0_0n" 0) "a_0" "b_1"))
(instance "th23w2" ("sum_0" "co_1" "a_0" "b_0"))
(instance "c2" ("co_1" "a_1" "b_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("ha__1_0n" 1)
("ha__0_0n" 1)
("n0__1_0n" 1)
("n0__0_0n" 1)
("n1__1_0n" 1)
("n1__0_0n" 1)
)
(instances
(instance "dr_xor2" (("n0__0_0n" 0) ("n0__1_0n" 0) ("n1__0_0n" 0) ("n1__1_0n" 0) "co_0" "co_1"))
(instance "dr_ha_bal" (("ha__0_0n" 0) ("ha__1_0n" 0) "ci_0" "ci_1" ("n1__0_0n" 0) ("n1__1_0n" 0) "sum_0" "sum_1"))
(instance "dr_ha_bal" ("a_0" "a_1" "b_0" "b_1" ("n0__0_0n" 0) ("n0__1_0n" 0) ("ha__0_0n" 0) ("ha__1_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_fa"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("minterm_0n" 8)
)
(instances
(instance "or4" ("co0" ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4)))
(instance "or4" ("co1" ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 7)))
(instance "or4" ("sum0" ("minterm_0n" 0) ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "or4" ("sum1" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4) ("minterm_0n" 7)))
(instance "c3" (("minterm_0n" 7) "a1" "b1" "ci1"))
(instance "c3" (("minterm_0n" 6) "a1" "b1" "ci0"))
(instance "c3" (("minterm_0n" 5) "a1" "b0" "ci1"))
(instance "c3" (("minterm_0n" 4) "a1" "b0" "ci0"))
(instance "c3" (("minterm_0n" 3) "a0" "b1" "ci1"))
(instance "c3" (("minterm_0n" 2) "a0" "b1" "ci0"))
(instance "c3" (("minterm_0n" 1) "a0" "b0" "ci1"))
(instance "c3" (("minterm_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_fa"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
)
(instances
(instance "th34w2" ("sum1" "co0" "a1" "b1" "ci1"))
(instance "th34w2" ("sum0" "co1" "a0" "b0" "ci0"))
(instance "th23" ("co1" "a1" "b1" "ci1"))
(instance "th23" ("co0" "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("co_1" ("n1_0n" 0) ("n2_0n" 0) ("n3_0n" 0)))
(instance "or2" ("sum_0" ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_1" "co_0" ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" ("co_0" "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p_bal"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "or3" ("co_0" "gnd" ("n0_0n" 0) "gnd"))
(instance "or3" ("co_1" ("n1_0n" 0) ("n2_0n" 0) ("n3_0n" 0)))
(instance "or2" ("sum_0" ("n1_0n" 0) ("n2_0n" 0)))
(instance "or2" ("sum_1" ("n0_0n" 0) ("n3_0n" 0)))
(instance "c2" (("n3_0n" 0) "a_1" "b_1"))
(instance "c2" (("n2_0n" 0) "a_1" "b_0"))
(instance "c2" (("n1_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_0" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_fa_p_ncl"
(ports
("a_0" input 1)
("a_1" input 1)
("b_0" input 1)
("b_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
)
(nets
("n0_0n" 1)
("n1_0n" 1)
("n2_0n" 1)
("n3_0n" 1)
)
(instances
(instance "th23w2" ("co_1" "sum_0" "a_0" "b_1"))
(instance "th23w2" ("sum_1" "co_0" "a_1" "b_1"))
(instance "c2" ("co_0" "a_0" "b_0"))
(instance "th23w2" ("sum_0" ("n0_0n" 0) "a_0" "b_1"))
(instance "c2" (("n0_0n" 0) "a_1" "b_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_fs"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("minterm_0n" 8)
)
(instances
(instance "or4" ("co1" ("minterm_0n" 0) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "or4" ("co0" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3) ("minterm_0n" 7)))
(instance "or4" ("sum1" ("minterm_0n" 0) ("minterm_0n" 3) ("minterm_0n" 5) ("minterm_0n" 6)))
(instance "or4" ("sum0" ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 4) ("minterm_0n" 7)))
(instance "c3" (("minterm_0n" 7) "a1" "b1" "ci1"))
(instance "c3" (("minterm_0n" 6) "a1" "b1" "ci0"))
(instance "c3" (("minterm_0n" 5) "a1" "b0" "ci1"))
(instance "c3" (("minterm_0n" 4) "a1" "b0" "ci0"))
(instance "c3" (("minterm_0n" 3) "a0" "b1" "ci1"))
(instance "c3" (("minterm_0n" 2) "a0" "b1" "ci0"))
(instance "c3" (("minterm_0n" 1) "a0" "b0" "ci1"))
(instance "c3" (("minterm_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_fs"
(ports
("a0" input 1)
("a1" input 1)
("b0" input 1)
("b1" input 1)
("ci0" input 1)
("ci1" input 1)
("co0" output 1)
("co1" output 1)
("sum0" output 1)
("sum1" output 1)
)
(nets
("cint_0n" 2)
)
(instances
(instance "th23" ("co1" ("cint_0n" 0) "b1" ("ci1_0n" 0)))
(instance "th23" ("co0" ("cint_0n" 1) "b0" ("ci0_0n" 0)))
(instance "th34w2" ("sum1" ("cint_0n" 0) "a1" "b1" "ci1"))
(instance "th34w2" ("sum0" ("cint_0n" 1) "a0" "b0" "ci0"))
(instance "th23" (("cint_0n" 1) "a1" "b1" "ci1"))
(instance "th23" (("cint_0n" 0) "a0" "b0" "ci0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ha"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 4)
)
(instances
(instance "or3" ("co_1" ("sopint_0n" 0) ("sopint_0n" 2) ("mint_0n" 11)))
(instance "or4" ("co_0" ("mint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 3) "sum_3"))
(instance "or4" ("sum_3" ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or2" ("sum_2" ("sopint_0n" 3) ("mint_0n" 11)))
(instance "or2" ("sum_1" ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "or2" ("sum_0" ("mint_0n" 0) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 3) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 10)))
(instance "or2" (("sopint_0n" 2) ("mint_0n" 6) ("mint_0n" 7)))
(instance "or2" (("sopint_0n" 1) ("mint_0n" 4) ("mint_0n" 5)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 14) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 13) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 12) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 11) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 9) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 6) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "or2" ("sum_3" ("mint_0n" 5) ("mint_0n" 6)))
(instance "or2" ("sum_2" ("mint_0n" 3) ("mint_0n" 4)))
(instance "or2" ("sum_1" ("mint_0n" 1) ("mint_0n" 2)))
(instance "or2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 4)
)
(instances
(instance "or4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "th23w2" ("sum_3" ("mint_0n" 3) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_1"))
(instance "th23w2" ("sum_2" ("mint_0n" 2) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "or2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or2" ("s_1" ("mint_0n" 4) "sum_3"))
(instance "or4" ("s_0" ("mint_0n" 0) "sum_1" ("mint_0n" 3) "co_1"))
(instance "or4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "or2" ("sum_3" ("mint_0n" 5) ("mint_0n" 6)))
(instance "or2" ("sum_2" ("mint_0n" 3) ("mint_0n" 4)))
(instance "or2" ("sum_1" ("mint_0n" 1) ("mint_0n" 2)))
(instance "or2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or2" ("s_1" ("mint_0n" 3) "sum_3"))
(instance "or4" ("s_0" ("mint_0n" 0) "sum_1" ("mint_0n" 2) "co_1"))
(instance "or4" ("co_0" ("mint_0n" 0) "sum_1" "sum_2" "sum_3"))
(instance "th23w2" ("sum_3" ("mint_0n" 4) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "or2" ("sum_2" ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "ci_1"))
(instance "or2" ("sum_0" ("mint_0n" 0) "co_1"))
(instance "c2" ("co_1" "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("halfsum_0n" 4)
("halfcar_0n" 4)
)
(instances
(instance "dr_xor2" (("halfcar_0n" 0) ("halfcar_0n" 1) ("halfcar_0n" 2) ("halfcar_0n" 3) "co_0" "co_1"))
(instance "oof_dims_ca" (("halfsum_0n" 0) ("halfsum_0n" 1) ("halfsum_0n" 2) ("halfsum_0n" 3) "ci_0" "ci_1" ("halfcar_0n" 2) ("halfcar_0n" 3) "sum_0" "sum_1" "sum_2" "sum_3"))
(instance "oof_ha" ("i0_0" "i0_1" "i0_2" "i0_3" "i1_0" "i1_1" "i1_2" "i1_3" ("halfcar_0n" 0) ("halfcar_0n" 1) ("halfsum_0n" 0) ("halfsum_0n" 1) ("halfsum_0n" 2) ("halfsum_0n" 3)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
)
(instances
(instance "or4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "or4" (("carrint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "or4" (("carrint_0n" 6) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "or4" (("carrint_0n" 5) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 21) ("minterm_0n" 22)))
(instance "or4" (("carrint_0n" 4) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "or4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "or4" (("carrint_0n" 3) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24)))
(instance "or4" (("carrint_0n" 2) ("minterm_0n" 9) ("minterm_0n" 10) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or4" (("carrint_0n" 1) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8)))
(instance "or4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "or2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "or4" (("sumint_0n" 7) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "or4" (("sumint_0n" 6) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "or4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "or4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "or2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "or4" (("sumint_0n" 3) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "or4" (("sumint_0n" 2) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "or2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "or4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "or4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fa_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
("overint_0n" 8)
)
(instances
(instance "or4" ("s_1" ("overint_0n" 4) ("overint_0n" 5) ("overint_0n" 6) ("overint_0n" 7)))
(instance "or4" (("overint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "or4" (("overint_0n" 6) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 23) ("minterm_0n" 24)))
(instance "or4" (("overint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 20)))
(instance "or4" (("overint_0n" 4) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 12)))
(instance "or4" ("s_0" ("overint_0n" 0) ("overint_0n" 1) ("overint_0n" 2) ("overint_0n" 3)))
(instance "or4" (("overint_0n" 3) ("minterm_0n" 19) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "or4" (("overint_0n" 2) ("minterm_0n" 11) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "or4" (("overint_0n" 1) ("minterm_0n" 7) ("minterm_0n" 8) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "or4" (("overint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "or4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "or4" (("carrint_0n" 7) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30) ("minterm_0n" 31)))
(instance "or4" (("carrint_0n" 6) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26) ("minterm_0n" 27)))
(instance "or4" (("carrint_0n" 5) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 21) ("minterm_0n" 22)))
(instance "or4" (("carrint_0n" 4) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "or4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "or4" (("carrint_0n" 3) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24)))
(instance "or4" (("carrint_0n" 2) ("minterm_0n" 9) ("minterm_0n" 10) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or4" (("carrint_0n" 1) ("minterm_0n" 4) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8)))
(instance "or4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3)))
(instance "or2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "or4" (("sumint_0n" 7) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "or4" (("sumint_0n" 6) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "or4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "or4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "or2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "or4" (("sumint_0n" 3) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "or4" (("sumint_0n" 2) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "or2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "or4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "or4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_fs"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("minterm_0n" 32)
("sumint_0n" 8)
("carrint_0n" 8)
)
(instances
(instance "or4" ("co_1" ("carrint_0n" 4) ("carrint_0n" 5) ("carrint_0n" 6) ("carrint_0n" 7)))
(instance "or4" (("carrint_0n" 7) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 23) ("minterm_0n" 31)))
(instance "or4" (("carrint_0n" 6) ("minterm_0n" 12) ("minterm_0n" 13) ("minterm_0n" 14) ("minterm_0n" 15)))
(instance "or4" (("carrint_0n" 5) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 7) ("minterm_0n" 11)))
(instance "or4" (("carrint_0n" 4) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 3) ("minterm_0n" 4)))
(instance "or4" ("co_0" ("carrint_0n" 0) ("carrint_0n" 1) ("carrint_0n" 2) ("carrint_0n" 3)))
(instance "or4" (("carrint_0n" 3) ("minterm_0n" 27) ("minterm_0n" 28) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "or4" (("carrint_0n" 2) ("minterm_0n" 20) ("minterm_0n" 24) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "or4" (("carrint_0n" 1) ("minterm_0n" 16) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 19)))
(instance "or4" (("carrint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 8) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "or2" ("sum_3" ("sumint_0n" 6) ("sumint_0n" 7)))
(instance "or4" (("sumint_0n" 7) ("minterm_0n" 21) ("minterm_0n" 22) ("minterm_0n" 24) ("minterm_0n" 31)))
(instance "or4" (("sumint_0n" 6) ("minterm_0n" 1) ("minterm_0n" 2) ("minterm_0n" 11) ("minterm_0n" 12)))
(instance "or2" ("sum_2" ("sumint_0n" 4) ("sumint_0n" 5)))
(instance "or4" (("sumint_0n" 5) ("minterm_0n" 16) ("minterm_0n" 23) ("minterm_0n" 25) ("minterm_0n" 26)))
(instance "or4" (("sumint_0n" 4) ("minterm_0n" 3) ("minterm_0n" 4) ("minterm_0n" 13) ("minterm_0n" 14)))
(instance "or2" ("sum_1" ("sumint_0n" 2) ("sumint_0n" 3)))
(instance "or4" (("sumint_0n" 3) ("minterm_0n" 17) ("minterm_0n" 18) ("minterm_0n" 27) ("minterm_0n" 28)))
(instance "or4" (("sumint_0n" 2) ("minterm_0n" 5) ("minterm_0n" 6) ("minterm_0n" 8) ("minterm_0n" 15)))
(instance "or2" ("sum_0" ("sumint_0n" 0) ("sumint_0n" 1)))
(instance "or4" (("sumint_0n" 1) ("minterm_0n" 19) ("minterm_0n" 20) ("minterm_0n" 29) ("minterm_0n" 30)))
(instance "or4" (("sumint_0n" 0) ("minterm_0n" 0) ("minterm_0n" 7) ("minterm_0n" 9) ("minterm_0n" 10)))
(instance "c3" (("minterm_0n" 31) "i0_3" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 30) "i0_3" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 29) "i0_3" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 28) "i0_3" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 27) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 26) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 25) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 24) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 23) "i0_2" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 22) "i0_2" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 21) "i0_2" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 20) "i0_2" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 19) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 18) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 17) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 16) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 15) "i0_1" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 14) "i0_1" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 13) "i0_1" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 12) "i0_1" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 11) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 10) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 9) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 8) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("minterm_0n" 7) "i0_0" "i1_3" "ci_1"))
(instance "c3" (("minterm_0n" 6) "i0_0" "i1_3" "ci_0"))
(instance "c3" (("minterm_0n" 5) "i0_0" "i1_2" "ci_1"))
(instance "c3" (("minterm_0n" 4) "i0_0" "i1_2" "ci_0"))
(instance "c3" (("minterm_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("minterm_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("minterm_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("minterm_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fa"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 6)
("assoc_0n" 6)
("eqv_0n" 4)
("fsum_0n" 4)
("fcar_0n" 2)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 0)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 1)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 0)))
(instance "or4" (("fcar_0n" 1) ("assoc_0n" 4) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "or4" (("fcar_0n" 0) ("assoc_0n" 0) ("assoc_0n" 1) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "or3" (("fsum_0n" 3) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 2)))
(instance "or3" (("fsum_0n" 2) ("assoc_0n" 1) ("eqv_0n" 1) ("eqv_0n" 3)))
(instance "or2" (("fsum_0n" 1) ("assoc_0n" 0) ("assoc_0n" 5)))
(instance "or2" (("fsum_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "c2" (("eqv_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("eqv_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("eqv_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("eqv_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" (("assoc_0n" 5) ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23w2" (("assoc_0n" 4) ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23w2" (("assoc_0n" 3) ("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("assoc_0n" 2) ("mint_0n" 2) "i0_3" "i1_0"))
(instance "th23w2" (("assoc_0n" 1) ("mint_0n" 1) "i0_2" "i1_0"))
(instance "th23w2" (("assoc_0n" 0) ("mint_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fa_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 6)
("assoc_0n" 6)
("eqv_0n" 4)
("fsum_0n" 4)
("fcar_0n" 2)
("fext_0n" 2)
("fshar_0n" 1)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("s_1" ("fext_0n" 1) "ci_0" "ci_1" ("fshar_0n" 0)))
(instance "th34w22" ("s_0" ("fext_0n" 0) "ci_1" "ci_0" ("fshar_0n" 0)))
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 0)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 1)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 0)))
(instance "or2" (("fshar_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "or4" (("fext_0n" 1) ("assoc_0n" 1) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "or4" (("fext_0n" 0) ("assoc_0n" 0) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "or4" (("fcar_0n" 1) ("assoc_0n" 4) ("assoc_0n" 5) ("eqv_0n" 2) ("eqv_0n" 3)))
(instance "or4" (("fcar_0n" 0) ("assoc_0n" 0) ("assoc_0n" 1) ("eqv_0n" 0) ("eqv_0n" 1)))
(instance "or3" (("fsum_0n" 3) ("assoc_0n" 4) ("eqv_0n" 0) ("eqv_0n" 2)))
(instance "or3" (("fsum_0n" 2) ("assoc_0n" 1) ("eqv_0n" 1) ("eqv_0n" 3)))
(instance "or2" (("fsum_0n" 1) ("assoc_0n" 0) ("assoc_0n" 5)))
(instance "or2" (("fsum_0n" 0) ("assoc_0n" 2) ("assoc_0n" 3)))
(instance "c2" (("eqv_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("eqv_0n" 2) "i0_2" "i1_2"))
(instance "c2" (("eqv_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("eqv_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" (("assoc_0n" 5) ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23w2" (("assoc_0n" 4) ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23w2" (("assoc_0n" 3) ("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("assoc_0n" 2) ("mint_0n" 2) "i0_3" "i1_0"))
(instance "th23w2" (("assoc_0n" 1) ("mint_0n" 1) "i0_2" "i1_0"))
(instance "th23w2" (("assoc_0n" 0) ("mint_0n" 0) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_fs"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("fsum_0n" 4)
("fcar_0n" 2)
("cint_0n" 2)
("sint_0n" 4)
)
(instances
(instance "th34w22" ("co_1" ("fcar_0n" 1) "ci_1" ("fsum_0n" 0) "ci_0"))
(instance "th34w22" ("co_0" ("fcar_0n" 0) "ci_0" ("fsum_0n" 0) "ci_1"))
(instance "th23w2" ("sum_3" ("sint_0n" 3) "ci_0" ("fsum_0n" 3)))
(instance "th23w2" ("sum_2" ("sint_0n" 2) "ci_0" ("fsum_0n" 2)))
(instance "th23w2" ("sum_1" ("sint_0n" 1) "ci_0" ("fsum_0n" 1)))
(instance "th23w2" ("sum_0" ("sint_0n" 0) "ci_0" ("fsum_0n" 0)))
(instance "c2" (("sint_0n" 3) "ci_1" ("fsum_0n" 0)))
(instance "c2" (("sint_0n" 2) "ci_1" ("fsum_0n" 3)))
(instance "c2" (("sint_0n" 1) "ci_1" ("fsum_0n" 2)))
(instance "c2" (("sint_0n" 0) "ci_1" ("fsum_0n" 1)))
(instance "or3" (("fcar_0n" 1) ("mint_0n" 7) ("mint_0n" 11) ("cint_0n" 1)))
(instance "or3" (("fcar_0n" 0) ("mint_0n" 13) ("mint_0n" 14) ("cint_0n" 0)))
(instance "or4" (("cint_0n" 1) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "or4" (("cint_0n" 0) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "or4" (("fsum_0n" 3) ("mint_0n" 1) ("mint_0n" 6) ("mint_0n" 11) ("mint_0n" 12)))
(instance "or4" (("fsum_0n" 2) ("mint_0n" 2) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 13)))
(instance "or4" (("fsum_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 9) ("mint_0n" 14)))
(instance "or4" (("fsum_0n" 0) ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 6)))
(instance "or2" ("sum_3" "co_0" ("mint_0n" 6)))
(instance "or2" ("sum_2" ("mint_0n" 4) ("mint_0n" 5)))
(instance "or2" ("sum_1" ("mint_0n" 2) ("mint_0n" 3)))
(instance "or2" ("sum_0" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 4)
)
(instances
(instance "or4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 3)))
(instance "or2" ("sum_3" "co_0" ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_3" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
(instance "th23w2" ("sum_2" ("mint_0n" 2) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_2" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_1"))
(instance "th23w2" ("sum_0" ("mint_0n" 0) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 7)
)
(instances
(instance "or3" ("s_1" "sum_3" "sum_2" ("mint_0n" 3)))
(instance "or2" ("s_0" "sum_0" ("mint_0n" 2)))
(instance "or4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 6)))
(instance "or2" ("sum_3" "co_0" ("mint_0n" 6)))
(instance "or2" ("sum_2" ("mint_0n" 4) ("mint_0n" 5)))
(instance "or2" ("sum_1" ("mint_0n" 2) ("mint_0n" 3)))
(instance "or2" ("sum_0" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 6) "i0_3" "ci_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "ci_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "ci_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 5)
)
(instances
(instance "or3" ("s_1" "sum_3" "sum_2" ("mint_0n" 3)))
(instance "or2" ("s_0" "sum_0" ("mint_0n" 2)))
(instance "or4" ("co_1" "sum_0" "sum_1" "sum_2" ("mint_0n" 4)))
(instance "or2" ("sum_3" "co_0" ("mint_0n" 4)))
(instance "c2" (("mint_0n" 4) "i0_3" "ci_1"))
(instance "c2" ("co_0" "i0_0" "ci_0"))
(instance "or2" ("sum_2" ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_3" "ci_0"))
(instance "c2" (("mint_0n" 2) "i0_2" "ci_1"))
(instance "th23w2" ("sum_1" ("mint_0n" 1) "i0_2" "ci_0"))
(instance "c2" (("mint_0n" 1) "i0_1" "ci_1"))
(instance "th23w2" ("sum_0" ("mint_0n" 0) "i0_1" "ci_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "ci_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 1)
)
(instances
(instance "or4" ("co_1" ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or4" ("co_0" ("mint_0n" 0) ("sopint_0n" 0) "sum_2" "sum_3"))
(instance "or4" ("sum_3" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or4" ("sum_2" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "or3" ("sum_1" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "or3" ("sum_0" ("mint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 3)
("sumint_0n" 6)
("carint_0n" 5)
)
(instances
(instance "th23w2" ("co_1" ("carint_0n" 3) ("carint_0n" 4) "ci_1"))
(instance "or3" (("carint_0n" 4) ("mint_0n" 0) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("carint_0n" 3) ("mint_0n" 0) "ci_0"))
(instance "or3" ("co_0" ("carint_0n" 2) "sum_2" "sum_3"))
(instance "th23w2" (("carint_0n" 2) ("carint_0n" 1) ("carint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 1) ("carint_0n" 0) ("sopint_0n" 1) "ci_0"))
(instance "c2" (("carint_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 4) ("sumint_0n" 5) "ci_0"))
(instance "or2" (("sumint_0n" 5) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("sumint_0n" 4) ("sopint_0n" 2) "ci_1"))
(instance "th23w2" ("sum_2" ("sumint_0n" 3) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sumint_0n" 2) "ci_1"))
(instance "or2" (("sumint_0n" 2) ("sopint_0n" 0) ("mint_0n" 3)))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("mint_0n" 4) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 0) "ci_0"))
(instance "c2" (("mint_0n" 4) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_1"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 2) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_3" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or2" ("s_1" ("sopint_0n" 2) ("mint_0n" 8)))
(instance "or4" ("s_0" "sum_1" "sum_0" ("sopint_0n" 1) ("mint_0n" 7)))
(instance "or4" ("co_1" ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or4" ("co_0" ("mint_0n" 0) ("sopint_0n" 0) "sum_2" "sum_3"))
(instance "or2" ("sum_3" ("mint_0n" 7) ("sopint_0n" 2)))
(instance "or3" (("sopint_0n" 2) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or2" ("sum_2" ("sopint_0n" 1) ("mint_0n" 8)))
(instance "or3" (("sopint_0n" 1) ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6)))
(instance "or3" ("sum_1" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "or3" ("sum_0" ("mint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 3)
("sumint_0n" 6)
("carint_0n" 5)
("exint_0n" 4)
)
(instances
(instance "th23w2" ("s_1" ("exint_0n" 3) ("mint_0n" 3) "ci_1"))
(instance "c2" (("exint_0n" 3) ("exint_0n" 2) "ci_0"))
(instance "or3" (("exint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "or3" ("s_0" "sum_1" "sum_0" ("exint_0n" 1)))
(instance "th23w2" (("exint_0n" 1) ("exint_0n" 0) ("mint_0n" 2) "ci_0"))
(instance "th23" (("exint_0n" 0) "ci_1" ("sopint_0n" 1) ("mint_0n" 2)))
(instance "th23w2" ("co_1" ("carint_0n" 3) ("carint_0n" 4) "ci_1"))
(instance "or3" (("carint_0n" 4) ("mint_0n" 0) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("carint_0n" 3) ("mint_0n" 0) "ci_0"))
(instance "or3" ("co_0" ("carint_0n" 2) "sum_2" "sum_3"))
(instance "th23w2" (("carint_0n" 2) ("carint_0n" 1) ("carint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 1) ("carint_0n" 0) ("sopint_0n" 1) "ci_0"))
(instance "c2" (("carint_0n" 0) "i0_0" "i1_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 4) ("sumint_0n" 5) "ci_0"))
(instance "or2" (("sumint_0n" 5) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("sumint_0n" 4) ("sopint_0n" 2) "ci_1"))
(instance "th23w2" ("sum_2" ("sumint_0n" 3) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sumint_0n" 2) "ci_1"))
(instance "or2" (("sumint_0n" 2) ("sopint_0n" 0) ("mint_0n" 4)))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("mint_0n" 5) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 0) "ci_0"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "or2" (("sopint_0n" 2) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_3" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 1)
)
(instances
(instance "or3" ("co_1" ("sopint_0n" 0) "sum_0" "sum_1"))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or4" ("co_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "or4" ("sum_3" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 15)))
(instance "or4" ("sum_2" ("mint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" ("sum_1" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or4" ("sum_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_pca"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 4)
("sumint_0n" 4)
("carint_0n" 2)
)
(instances
(instance "th23w2" ("co_1" ("carint_0n" 1) ("mint_0n" 1) "ci_0"))
(instance "th23" (("carint_0n" 1) ("sopint_0n" 3) ("mint_0n" 1) "ci_1"))
(instance "th23w2" ("co_0" ("carint_0n" 0) ("mint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 0) ("sopint_0n" 1) ("mint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_3" ("sumint_0n" 3) ("sopint_0n" 0) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_2" ("sumint_0n" 2) ("sopint_0n" 3) "ci_1"))
(instance "c2" (("sumint_0n" 2) ("sopint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sopint_0n" 2) "ci_1"))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 3) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 4) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "or2" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "or3" ("s_1" ("sopint_0n" 1) "sum_2" "sum_3"))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or4" ("s_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "or3" ("co_1" ("sopint_0n" 0) "sum_0" "sum_1"))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14) ("mint_0n" 15)))
(instance "or4" ("co_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4)))
(instance "or4" ("sum_3" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 15)))
(instance "or4" ("sum_2" ("mint_0n" 0) ("mint_0n" 11) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" ("sum_1" ("mint_0n" 7) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12)))
(instance "or4" ("sum_0" ("mint_0n" 3) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "c3" (("mint_0n" 15) "i0_3" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 14) "i0_3" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 13) "i0_3" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 12) "i0_3" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 11) "i0_2" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 10) "i0_2" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 9) "i0_2" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 8) "i0_2" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 7) "i0_1" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 6) "i0_1" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 5) "i0_1" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 4) "i0_1" "i1_0" "ci_0"))
(instance "c3" (("mint_0n" 3) "i0_0" "i1_1" "ci_1"))
(instance "c3" (("mint_0n" 2) "i0_0" "i1_1" "ci_0"))
(instance "c3" (("mint_0n" 1) "i0_0" "i1_0" "ci_1"))
(instance "c3" (("mint_0n" 0) "i0_0" "i1_0" "ci_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_pca_se"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("ci_0" input 1)
("ci_1" input 1)
("co_0" output 1)
("co_1" output 1)
("sum_0" output 1)
("sum_1" output 1)
("sum_2" output 1)
("sum_3" output 1)
("s_0" output 1)
("s_1" output 1)
)
(nets
("mint_0n" 5)
("sopint_0n" 4)
("sumint_0n" 4)
("carint_0n" 2)
("exint_0n" 3)
)
(instances
(instance "or3" ("s_1" "sum_2" "sum_3" ("exint_0n" 2)))
(instance "th23w2" (("exint_0n" 2) ("exint_0n" 1) ("mint_0n" 4) "ci_1"))
(instance "th23" (("exint_0n" 1) "ci_0" ("sopint_0n" 3) ("mint_0n" 4)))
(instance "th23w2" ("s_0" ("exint_0n" 0) ("mint_0n" 3) "ci_0"))
(instance "th23" (("exint_0n" 0) "ci_1" ("sopint_0n" 1) ("mint_0n" 3)))
(instance "th23w2" ("co_1" ("carint_0n" 1) ("mint_0n" 1) "ci_0"))
(instance "th23" (("carint_0n" 1) ("sopint_0n" 3) ("mint_0n" 1) "ci_1"))
(instance "th23w2" ("co_0" ("carint_0n" 0) ("mint_0n" 0) "ci_1"))
(instance "th23" (("carint_0n" 0) ("sopint_0n" 1) ("mint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_3" ("sumint_0n" 3) ("sopint_0n" 0) "ci_1"))
(instance "c2" (("sumint_0n" 3) ("sopint_0n" 1) "ci_0"))
(instance "th23w2" ("sum_2" ("sumint_0n" 2) ("sopint_0n" 3) "ci_1"))
(instance "c2" (("sumint_0n" 2) ("sopint_0n" 0) "ci_0"))
(instance "th23w2" ("sum_1" ("sumint_0n" 1) ("sopint_0n" 2) "ci_1"))
(instance "c2" (("sumint_0n" 1) ("sopint_0n" 3) "ci_0"))
(instance "th23w2" ("sum_0" ("sumint_0n" 0) ("sopint_0n" 1) "ci_1"))
(instance "c2" (("sumint_0n" 0) ("sopint_0n" 2) "ci_0"))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "or2" (("sopint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "or2" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 15)
("sopint_0n" 2)
)
(instances
(instance "or3" ("q0_2" ("mint_0n" 10) ("mint_0n" 11) ("mint_0n" 14)))
(instance "or3" ("q0_1" ("mint_0n" 5) ("mint_0n" 7) ("mint_0n" 13)))
(instance "or3" ("q0_0" ("mint_0n" 12) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 4) ("mint_0n" 6) ("mint_0n" 8) ("mint_0n" 9)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" ("q0_3" "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_and2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_3" "i0_3" "i1_3"))
(instance "th23w2" ("q0_2" ("mint_0n" 5) "i0_3" "i1_2"))
(instance "th23" (("mint_0n" 5) "i0_2" "i1_2" "i1_3"))
(instance "th23w2" ("q0_1" ("mint_0n" 4) "i0_3" "i1_1"))
(instance "th23" (("mint_0n" 4) "i0_1" "i1_1" "i1_3"))
(instance "th23w2" ("q0_0" ("sopint_0n" 0) "i0_3" "i1_0"))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_1" "i1_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_0" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 15)
("sopint_0n" 2)
)
(instances
(instance "or3" ("q0_3" ("mint_0n" 14) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 10) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 8)))
(instance "or3" ("q0_2" ("mint_0n" 1) ("mint_0n" 7) ("mint_0n" 9)))
(instance "or3" ("q0_1" ("mint_0n" 0) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 11) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 7) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_1"))
(instance "c2" ("q0_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_or2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_3" ("sopint_0n" 0) "i0_0" "i1_3"))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "th23" (("mint_0n" 5) "i0_3" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 4) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_1" "i1_3"))
(instance "th23" (("mint_0n" 2) "i0_1" "i1_2" "i1_3"))
(instance "th23w2" ("q0_2" ("mint_0n" 1) "i0_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_2"))
(instance "th23w2" ("q0_1" ("mint_0n" 0) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
(instance "c2" ("q0_0" "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 16)
)
(instances
(instance "or4" ("q0_3" ("mint_0n" 3) ("mint_0n" 6) ("mint_0n" 9) ("mint_0n" 12)))
(instance "or4" ("q0_2" ("mint_0n" 2) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 13)))
(instance "or4" ("q0_1" ("mint_0n" 1) ("mint_0n" 4) ("mint_0n" 11) ("mint_0n" 14)))
(instance "or4" ("q0_0" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_xor2"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
("q0_3" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 8)
)
(instances
(instance "or2" ("q0_3" ("sopint_0n" 6) ("sopint_0n" 7)))
(instance "th23w2" (("sopint_0n" 7) ("mint_0n" 7) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_2"))
(instance "th23w2" (("sopint_0n" 6) ("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 6) "i0_0" "i1_3"))
(instance "or2" ("q0_2" ("sopint_0n" 4) ("sopint_0n" 5)))
(instance "th23w2" (("sopint_0n" 5) ("mint_0n" 5) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_3"))
(instance "th23w2" (("sopint_0n" 4) ("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_2"))
(instance "or2" ("q0_1" ("sopint_0n" 2) ("sopint_0n" 3)))
(instance "th23w2" (("sopint_0n" 3) ("mint_0n" 3) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_3"))
(instance "th23w2" (("sopint_0n" 2) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "or2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or4" ("q0_1" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "or3" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "or4" (("sopint_0n" 2) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 9)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 2)
)
(instances
(instance "or2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 5) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 4) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_0"))
(instance "or4" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th34w2" (("mint_0n" 3) "i0_3" "i1_1" "i1_1" "i1_2"))
(instance "th34w2" (("mint_0n" 2) "i0_2" "i1_0" "i1_1" "i1_3"))
(instance "th34w2" (("mint_0n" 1) "i0_1" "i1_0" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 0) "i0_0" "i1_1" "i1_2" "i1_3"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 0) ("mint_0n" 3)))
(instance "or3" ("q0_0" ("mint_0n" 1) ("mint_0n" 2) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_equal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q1_0" output 1)
("q1_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_1" ("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_0"))
(instance "or2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_1" "i1_0"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_2" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or3" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1) ("sopint_0n" 2)))
(instance "or4" (("sopint_0n" 2) ("mint_0n" 11) ("mint_0n" 12) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 8) ("mint_0n" 9)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4)))
(instance "or4" ("q0_0" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
("sopint_0n" 2)
)
(instances
(instance "or4" ("q0_1" ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "th34w2" (("mint_0n" 5) "i0_3" "i1_1" "i1_1" "i1_2"))
(instance "th34w2" (("mint_0n" 4) "i0_2" "i1_0" "i1_1" "i1_3"))
(instance "th34w2" (("mint_0n" 3) "i0_1" "i1_0" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 2) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "or2" ("q0_0" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 1) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 0) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or3" ("q0_1" ("mint_0n" 1) ("mint_0n" 2) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "or2" ("q0_0" ("mint_0n" 0) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_inequal"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 2)
)
(instances
(instance "or2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 2) "i0_1" "i1_0"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "or3" ("q0_2" ("sopint_0n" 1) ("mint_0n" 7) ("mint_0n" 11)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "or4" ("q0_1" ("mint_0n" 0) ("mint_0n" 5) ("mint_0n" 10) ("mint_0n" 15)))
(instance "or3" ("q0_0" ("sopint_0n" 0) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 2)
)
(instances
(instance "or3" ("q0_2" ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 6) "i0_1" "i1_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "or2" ("q0_1" ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "th23w2" (("sopint_0n" 1) ("mint_0n" 4) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_1"))
(instance "th23w2" (("sopint_0n" 0) ("mint_0n" 3) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_0"))
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th34w2" (("mint_0n" 2) "i0_3" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 0) ("mint_0n" 2)))
(instance "or2" ("q0_0" ("mint_0n" 6) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ineq_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_0"))
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_ineq_sgn_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 0) ("mint_0n" 2)))
(instance "or2" ("q0_2" ("mint_0n" 6) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_ineq_sgn_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "or3" ("q0_2" ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "th23" (("mint_0n" 3) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 2) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 1) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or3" ("q0_1" ("sopint_0n" 2) ("mint_0n" 7) ("mint_0n" 11)))
(instance "or4" (("sopint_0n" 2) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3) ("mint_0n" 6)))
(instance "or4" ("q0_0" ("mint_0n" 14) ("mint_0n" 15) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 9) ("mint_0n" 10) ("mint_0n" 12) ("mint_0n" 13)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 8)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or3" (("q0__1_0n" 0) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_0" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 6) "i0_1" "i1_2" "i1_3"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_3"))
(instance "or3" ("q0_0" ("mint_0n" 3) ("mint_0n" 4) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 4) "i0_3" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 3) "i0_3" "i1_0" "i1_1"))
(instance "th34w2" (("mint_0n" 2) "i0_2" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_1" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 16)
("sopint_0n" 3)
)
(instances
(instance "or3" ("q0_1" ("sopint_0n" 2) ("mint_0n" 13) ("mint_0n" 14)))
(instance "or4" (("sopint_0n" 2) ("mint_0n" 4) ("mint_0n" 8) ("mint_0n" 9) ("mint_0n" 12)))
(instance "or4" ("q0_0" ("mint_0n" 11) ("mint_0n" 15) ("sopint_0n" 0) ("sopint_0n" 1)))
(instance "or4" (("sopint_0n" 1) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7) ("mint_0n" 10)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 15) "i0_3" "i1_3"))
(instance "c2" (("mint_0n" 14) "i0_3" "i1_2"))
(instance "c2" (("mint_0n" 13) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 12) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 11) "i0_2" "i1_3"))
(instance "c2" (("mint_0n" 10) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 9) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 8) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 7) "i0_1" "i1_3"))
(instance "c2" (("mint_0n" 6) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_0" "i1_3"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("i1_3" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or3" ("q0_1" ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "th34w2" (("mint_0n" 7) "i0_3" "i1_0" "i1_1" "i1_2"))
(instance "th23" (("mint_0n" 6) "i0_2" "i1_0" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_0"))
(instance "or3" ("q0_0" ("mint_0n" 3) ("mint_0n" 4) ("sopint_0n" 0)))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 4) "i0_3" "i1_3"))
(instance "th23" (("mint_0n" 3) "i0_2" "i1_2" "i1_3"))
(instance "th34w2" (("mint_0n" 2) "i0_1" "i1_1" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 1) "i0_0" "i1_2" "i1_3"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 7)
("sopint_0n" 1)
)
(instances
(instance "or4" ("q0_0" ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "th23w2" ("q0_0" ("sopint_0n" 0) "i0_0" "i1_0"))
(instance "or3" (("sopint_0n" 0) ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 8)
("sopint_0n" 1)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 7) ("sopint_0n" 0)))
(instance "or4" (("sopint_0n" 0) ("mint_0n" 2) ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6)))
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_3" "i1_1"))
(instance "c2" (("mint_0n" 6) "i0_3" "i1_0"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 4) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oof_dr_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i0_3" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
("sopint_0n" 1)
)
(instances
(instance "th23w2" ("q0_1" ("sopint_0n" 0) "i0_1" "i1_0"))
(instance "or2" (("sopint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "th23" (("mint_0n" 2) "i0_3" "i1_0" "i1_1"))
(instance "th23" (("mint_0n" 1) "i0_2" "i1_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "or2" ("q0_1" ("mint_0n" 0) ("mint_0n" 1)))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_1"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_2" "i0_0" "i1_1"))
(instance "th23w2" ("q0_1" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
(instance "c2" ("q0_0" "i0_1" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 3)
)
(instances
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_lt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_0" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_0" "i1_0"))
(instance "th23" (("mint_0n" 0) "i0_1" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_dims_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 2) "i0_1" "i1_1"))
(instance "c2" ("q0_1" "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_ncl_gt"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 1)
)
(instances
(instance "c2" ("q0_1" "i0_1" "i1_0"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_1"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_oot_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 6)
)
(instances
(instance "or3" ("q0_1" ("mint_0n" 3) ("mint_0n" 4) ("mint_0n" 5)))
(instance "or3" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2)))
(instance "c2" (("mint_0n" 5) "i0_1" "i1_2"))
(instance "c2" (("mint_0n" 4) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 1) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_oot_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q0_1" ("mint_0n" 1) "i0_0" "i1_2"))
(instance "th23" (("mint_0n" 1) "i0_1" "i1_1" "i1_2"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_0"))
(instance "th23" (("mint_0n" 0) "i0_0" "i1_0" "i1_1"))
)
(attributes (cell-type "helper"))
)
(circuit "oot_dims_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 9)
)
(instances
(instance "or4" ("q0_2" ("mint_0n" 4) ("mint_0n" 5) ("mint_0n" 6) ("mint_0n" 7)))
(instance "or4" ("q0_0" ("mint_0n" 0) ("mint_0n" 1) ("mint_0n" 2) ("mint_0n" 3)))
(instance "c2" (("mint_0n" 7) "i0_2" "i1_2"))
(instance "c2" (("mint_0n" 6) "i0_2" "i1_1"))
(instance "c2" (("mint_0n" 5) "i0_2" "i1_0"))
(instance "c2" (("mint_0n" 4) "i0_1" "i1_2"))
(instance "c2" ("q0_1" "i0_1" "i1_1"))
(instance "c2" (("mint_0n" 3) "i0_1" "i1_0"))
(instance "c2" (("mint_0n" 2) "i0_0" "i1_2"))
(instance "c2" (("mint_0n" 1) "i0_0" "i1_1"))
(instance "c2" (("mint_0n" 0) "i0_0" "i1_0"))
)
(attributes (cell-type "helper"))
)
(circuit "oot_ncl_comp"
(ports
("i0_0" input 1)
("i0_1" input 1)
("i0_2" input 1)
("i1_0" input 1)
("i1_1" input 1)
("i1_2" input 1)
("q0_0" output 1)
("q0_1" output 1)
("q0_2" output 1)
)
(nets
("mint_0n" 2)
)
(instances
(instance "th23w2" ("q0_2" ("mint_0n" 1) "i0_1" "i1_2"))
(instance "th34w2" (("mint_0n" 1) "i0_2" "i1_0" "i1_1" "i1_2"))
(instance "c2" ("q0_1" "i0_1" "i1_1"))
(instance "th23w2" ("q0_0" ("mint_0n" 0) "i0_1" "i1_0"))
(instance "th34w2" (("mint_0n" 0) "i0_0" "i1_0" "i1_1" "i1_2"))
)
(attributes (cell-type "helper"))
)
(circuit "dr_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
)
(instances
(instance "ao22" ("in_a" "in_0" "out_0" "in_1" "out_1"))
(instance "nor2" ("out_0" "in_1" "out_1"))
(instance "nor2" ("out_1" "in_0" "out_0"))
)
(attributes (simulation-initialise ("out_0" 1)) (cell-type "helper"))
)
(circuit "dr_spacer_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("phase_one_0n" 2)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "or2" ("in_a" ("phase_one_0n" 0) ("phase_one_0n" 1)))
(instance "or2" (("outcomp_0n" 0) "out_0" "out_1"))
(instance "or2" (("incomp_0n" 0) "in_0" "in_1"))
(instance "nor3" ("out_1" ("incomp_0n" 0) ("phase_one_0n" 1) "out_0"))
(instance "nor3" ("out_0" ("incomp_0n" 0) ("phase_one_0n" 0) "out_1"))
(instance "nor3" (("phase_one_0n" 1) ("outcomp_0n" 0) "in_1" ("phase_one_0n" 0)))
(instance "nor3" (("phase_one_0n" 0) ("outcomp_0n" 0) "in_0" ("phase_one_0n" 1)))
)
(attributes (simulation-initialise ("out_0" 1)) (cell-type "helper"))
)
(circuit "dr_ncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("phase_one_0n" 2)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "or2" ("in_a" ("phase_one_0n" 0) ("phase_one_0n" 1)))
(instance "nor2" (("outcomp_0n" 0) "out_0" "out_1"))
(instance "nor2" (("incomp_0n" 0) "in_0" "in_1"))
(instance "c2" ("out_1" ("phase_one_0n" 1) ("incomp_0n" 0)))
(instance "c2" ("out_0" ("phase_one_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("phase_one_0n" 1) "in_1" ("outcomp_0n" 0)))
(instance "c2" (("phase_one_0n" 0) "in_0" ("outcomp_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "dr_tncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_a" output 1)
("out_r" input 1)
("out_0" output 1)
("out_1" output 1)
)
(nets
("write_sel_0n" 2)
("phase_one_0n" 2)
("phase_two_0n" 2)
("read_store_0n" 2)
("wrcomp_0n" 1)
("incomp_0n" 1)
("pocomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "c2" ("in_a" ("pocomp_0n" 0) ("wrcomp_0n" 0)))
(instance "or2" (("pocomp_0n" 0) ("phase_one_0n" 0) ("phase_one_0n" 1)))
(instance "nor2" (("outcomp_0n" 0) ("phase_two_0n" 0) ("phase_two_0n" 1)))
(instance "nor2" (("incomp_0n" 0) ("write_sel_0n" 0) ("write_sel_0n" 1)))
(instance "or2" (("wrcomp_0n" 0) "in_0" "in_1"))
(instance "c2" ("out_1" ("read_store_0n" 1) ("pocomp_0n" 0)))
(instance "c2" ("out_0" ("read_store_0n" 0) ("pocomp_0n" 0)))
(instance "c2" (("read_store_0n" 1) ("phase_two_0n" 1) "out_r"))
(instance "c2" (("read_store_0n" 0) ("phase_two_0n" 0) "out_r"))
(instance "c2" (("phase_two_0n" 1) ("phase_one_0n" 1) ("incomp_0n" 0)))
(instance "c2" (("phase_two_0n" 0) ("phase_one_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("phase_one_0n" 1) ("write_sel_0n" 1) ("outcomp_0n" 0)))
(instance "c2" (("phase_one_0n" 0) ("write_sel_0n" 0) ("outcomp_0n" 0)))
(instance "or2" (("write_sel_0n" 1) "in_1" ("read_store_0n" 1)))
(instance "or2" (("write_sel_0n" 0) "in_0" ("read_store_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("inp__nor_0n" 4)
("cross__na_0n" 2)
("nor__latch_0n" 4)
("group__na_0n" 4)
("ack__na_0n" 2)
("ph__4_0n" 4)
)
(instances
(instance "or2" ("in_a" ("ack__na_0n" 0) ("ack__na_0n" 1)))
(instance "nand2" (("ack__na_0n" 1) ("group__na_0n" 2) ("group__na_0n" 3)))
(instance "nand2" (("ack__na_0n" 0) ("group__na_0n" 0) ("group__na_0n" 1)))
(instance "nand2" (("group__na_0n" 3) "in_3" ("nor__latch_0n" 3)))
(instance "nand2" (("group__na_0n" 2) "in_2" ("nor__latch_0n" 2)))
(instance "nand2" (("group__na_0n" 1) "in_1" ("nor__latch_0n" 1)))
(instance "nand2" (("group__na_0n" 0) "in_0" ("nor__latch_0n" 0)))
(instance "nor2" (("nor__latch_0n" 3) ("cross__na_0n" 0) "out_2"))
(instance "nor2" (("nor__latch_0n" 2) ("cross__na_0n" 0) "out_3"))
(instance "nor2" (("nor__latch_0n" 1) ("cross__na_0n" 1) "out_0"))
(instance "nor2" (("nor__latch_0n" 0) ("cross__na_0n" 1) "out_1"))
(instance "nand2" (("cross__na_0n" 1) ("inp__nor_0n" 2) ("inp__nor_0n" 3)))
(instance "nand2" (("cross__na_0n" 0) ("inp__nor_0n" 0) ("inp__nor_0n" 1)))
(instance "inv" ("out_3" ("inp__nor_0n" 3)))
(instance "inv" ("out_2" ("inp__nor_0n" 2)))
(instance "inv" ("out_1" ("inp__nor_0n" 1)))
(instance "inv" ("out_0" ("inp__nor_0n" 0)))
(instance "nor2" (("inp__nor_0n" 3) "in_3" ("nor__latch_0n" 3)))
(instance "nor2" (("inp__nor_0n" 2) "in_2" ("nor__latch_0n" 2)))
(instance "nor2" (("inp__nor_0n" 1) "in_1" ("nor__latch_0n" 1)))
(instance "nor2" (("inp__nor_0n" 0) "in_0" ("nor__latch_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_ncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("_phase_one_0n" 4)
("incomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "or4" ("in_a" ("_phase_one_0n" 0) ("_phase_one_0n" 1) ("_phase_one_0n" 2) ("_phase_one_0n" 3)))
(instance "nor4" (("outcomp_0n" 0) "out_0" "out_1" "out_2" "out_3"))
(instance "nor4" (("incomp_0n" 0) "in_0" "in_1" "in_2" "in_3"))
(instance "c2" ("out_3" ("_phase_one_0n" 3) ("incomp_0n" 0)))
(instance "c2" ("out_2" ("_phase_one_0n" 2) ("incomp_0n" 0)))
(instance "c2" ("out_1" ("_phase_one_0n" 1) ("incomp_0n" 0)))
(instance "c2" ("out_0" ("_phase_one_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 3) "in_3" ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 2) "in_2" ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 1) "in_1" ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 0) "in_0" ("outcomp_0n" 0)))
)
(attributes (cell-type "helper"))
)
(circuit "oof_tncl_latch"
(ports
("in_0" input 1)
("in_1" input 1)
("in_2" input 1)
("in_3" input 1)
("in_a" output 1)
("out_r" input 1)
("out_0" output 1)
("out_1" output 1)
("out_2" output 1)
("out_3" output 1)
)
(nets
("_write_sel_0n" 4)
("_phase_one_0n" 4)
("_phase_two_0n" 4)
("_read_store_0n" 4)
("wrcomp_0n" 1)
("incomp_0n" 1)
("pocomp_0n" 1)
("outcomp_0n" 1)
)
(instances
(instance "c2" ("in_a" ("pocomp_0n" 0) ("wrcomp_0n" 0)))
(instance "or4" (("pocomp_0n" 0) ("_phase_one_0n" 0) ("_phase_one_0n" 1) ("_phase_one_0n" 2) ("_phase_one_0n" 3)))
(instance "nor4" (("outcomp_0n" 0) ("_phase_two_0n" 0) ("_phase_two_0n" 1) ("_phase_two_0n" 2) ("_phase_two_0n" 3)))
(instance "nor4" (("incomp_0n" 0) ("_write_sel_0n" 0) ("_write_sel_0n" 1) ("_write_sel_0n" 2) ("_write_sel_0n" 3)))
(instance "or4" (("wrcomp_0n" 0) "in_0" "in_1" "in_2" "in_3"))
(instance "c2" ("out_3" ("_read_store_0n" 3) ("pocomp_0n" 0)))
(instance "c2" ("out_2" ("_read_store_0n" 2) ("pocomp_0n" 0)))
(instance "c2" ("out_1" ("_read_store_0n" 1) ("pocomp_0n" 0)))
(instance "c2" ("out_0" ("_read_store_0n" 0) ("pocomp_0n" 0)))
(instance "c2" (("_read_store_0n" 3) ("_phase_two_0n" 3) "out_r"))
(instance "c2" (("_read_store_0n" 2) ("_phase_two_0n" 2) "out_r"))
(instance "c2" (("_read_store_0n" 1) ("_phase_two_0n" 1) "out_r"))
(instance "c2" (("_read_store_0n" 0) ("_phase_two_0n" 0) "out_r"))
(instance "c2" (("_phase_two_0n" 3) ("_phase_one_0n" 3) ("incomp_0n" 0)))
(instance "c2" (("_phase_two_0n" 2) ("_phase_one_0n" 2) ("incomp_0n" 0)))
(instance "c2" (("_phase_two_0n" 1) ("_phase_one_0n" 1) ("incomp_0n" 0)))
(instance "c2" (("_phase_two_0n" 0) ("_phase_one_0n" 0) ("incomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 3) ("_write_sel_0n" 3) ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 2) ("_write_sel_0n" 2) ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 1) ("_write_sel_0n" 1) ("outcomp_0n" 0)))
(instance "c2" (("_phase_one_0n" 0) ("_write_sel_0n" 0) ("outcomp_0n" 0)))
(instance "or2" (("_write_sel_0n" 3) "in_3" ("_read_store_0n" 3)))
(instance "or2" (("_write_sel_0n" 2) "in_2" ("_read_store_0n" 2)))
(instance "or2" (("_write_sel_0n" 1) "in_1" ("_read_store_0n" 1)))
(instance "or2" (("_write_sel_0n" 0) "in_0" ("_read_store_0n" 0)))
)
(attributes (cell-type "helper"))
)
balsa-tech-xilinx/xilinx/gate-mappings0000644003172000014400000002757610212061546020355 0ustar tomswapt00000000000000;;;
;;; `gate-mappings'
;;; Abstract->concrete gate mappings, for Xilinx 'Generic' technology
;;;
;;; 05 Mar 2004, Sam Taylor
;;; 02 Jul 1999, Andrew Bardsley
;;;
;;; This file has lists of (abs-gate-name default-real-gate . weighted-real-gates)
;;; The default real gate is used where nodal load management is not used and has the form:
;;; (gate-name . pin-mappings)
;;; The weighted-real-gates have the form:
;;; (output-drive gate-name . pin-mappings)
;;; The pin-mappings are lists of integers mapping abstract gate pin numbers to real gate pin
;;; numbers. The integers correspond to abstract gate pin positions (0 based) and their position
;;; to the position of that pin in the real gate. eg.
;;; (0 "q1and2d0" 2 1 0) is a drive 0 2-input and gate where pin 2 of the abstract gate (in2) is
;;; pin 0 of the real gate.
;;; and{n}: out,in1,in2...
("and2" ("and2" 0 1 2) (1 "and2"))
("and3" ("and3" 0 1 2 3) (1 "and3"))
("and4" ("and4" 0 1 2 3 4) (1 "and4"))
("and5" ("and5" 0 1 2 3 4 5) (1 "and5"))
;;; nand{n}: out,in1,in2...
("nand2" ("nand2" 0 1 2) (1 "nand2"))
("nand3" ("nand3" 0 1 2 3) (1 "nand3"))
("nand4" ("nand4" 0 1 2 3 4) (1 "nand4"))
("nand5" ("nand5" 0 1 2 3 4 5) (1 "nand5"))
;;; or{n}: out,in1,in2...
("or2" ("or2" 0 1 2) (1 "or2"))
("or3" ("or3" 0 1 2 3) (1 "or3"))
("or4" ("or4" 0 1 2 3 4) (1 "or4"))
("or5" ("or5" 0 1 2 3 4 5) (1 "or5"))
;;; nor{n}: out,in1,in2...
("nor2" ("nor2" 0 1 2) (1 "nor2"))
("nor3" ("nor3" 0 1 2 3) (1 "nor3"))
("nor4" ("nor4" 0 1 2 3 4) (1 "nor4"))
("nor5" ("nor5" 0 1 2 3 4 5) (1 "nor5"))
;;; xor2: out,in1,in2
("xor2" ("xor2" 0 1 2) (1 "xor2"))
;;; xnor2: out,in1,in2
("xnor2" ("xnor2" 0 1 2) (1 "xnor2"))
;;; inv: out,in
("inv" ("inv" 0 1) (1 "inv"))
;;; NB. buf is a driving buffer not a logical buffer
;;; buf: out,in
("buf" ("buff" 0 1) (1 "buff") (2 "BU2") (3 "BU3") (4 "BU4") (8 "BU8"))
("suggested-buffer" ("buff" 0 1) (1 "buff"))
;;; NB. connect is a logical buffer
;;; connect: out,in
("connect" ("buff" 0 1) (1 "buff"))
;;; latch: in,out,enable
("latch" ("fd" 2 0 1) (1 "fd"))
;;; Edge Triggered Flip Flop with async clear
("edge-dff-clr" ("fdc" 3 1 2 0) (1 "fdc"))
("adder" ("balsa_fa" 0 1 2 3 4 5 6 7) (1 "balsa_fa"))
;;; mutex: inA,inB,outA,outB
;;; mutual exclusion unit
("mutex" ("mutex1" 2 3 0 1) (1 "mutex1"))
;;; Helper Cells
("and-or22" ("ao22" 0 1 2 3 4) (1 "ao22"))
("and-or-invert22" ("aoi22" 0 1 2 3 4) (1 "aoi22"))
("and-or222" ("ao222" 0 1 2 3 4 5 6) (1 "ao222"))
("and-or-invert222" ("aoi222" 0 1 2 3 4 5 6) (1 "aoi222"))
("set-reset-flip-flop" ("srff" 0 1 2 3) (1 "srff"))
("mux2" ("mux2" 0 1 2 3) (1 "mux2"))
("nmux2" ("nmux2" 0 1 2 3) (1 "nmux2"))
("single-rail-full-adder" ("balsa_fa" 0 1 2 3 4 5 6 7) (1 "balsa_fa"))
("c-element2" ("c2" 0 1 2) (1 "c2"))
("c-element3" ("c3" 0 1 2 3) (1 "c3"))
("inverted-c-element" ("nc2" 0 1 2) (1 "nc2"))
("inverted-assym-c-element" ("nc2p" 0 1 2) (1 "nc2p"))
("demux2" ("demux2" 0 1 2 3) (1 "demux2"))
("s-element" ("selem" 0 1 2 3) (1 "selem"))
("th22" ("th22" 0 1 2) (1 "th22"))
("th33" ("th33" 0 1 2 3) (1 "th33"))
("th23" ("th23" 0 1 2 3) (1 "th23"))
("th23w2" ("th23w2" 0 1 2 3) (1 "th23w2"))
("th24" ("th24" 0 1 2 3 4) (1 "th24"))
("th24w2" ("th24w2" 0 1 2 3 4) (1 "th24w2"))
("th24w22" ("th24w22" 0 1 2 3 4) (1 "th24w22"))
("th33w2" ("th33w2" 0 1 2 3) (1 "th33w2"))
("th34" ("th34" 0 1 2 3 4) (1 "th34"))
("th34w2" ("th34w2" 0 1 2 3 4) (1 "th34w2"))
("th34w22" ("th34w22" 0 1 2 3 4) (1 "th34w22"))
("dual-rail-and2" ("dr_and2" 0 1 2 3 4 5) (1 "dr_and2"))
("dual-rail-and2-bal" ("dr_and2_bal" 0 1 2 3 4 5) (1 "dr_and2_bal"))
("dual-rail-and2-ncl" ("dr_and2_ncl" 0 1 2 3 4 5) (1 "dr_and2_ncl"))
("dual-rail-or2" ("dr_or2" 0 1 2 3 4 5) (1 "dr_or2"))
("dual-rail-or2-bal" ("dr_or2_bal" 0 1 2 3 4 5) (1 "dr_or2_bal"))
("dual-rail-or2-ncl" ("dr_or2_ncl" 0 1 2 3 4 5) (1 "dr_or2_ncl"))
("dual-rail-nor2" ("dr_nor2" 0 1 2 3 4 5) (1 "dr_nor2"))
("dual-rail-nor2-ncl" ("dr_nor2_ncl" 0 1 2 3 4 5) (1 "dr_nor2_ncl"))
("dual-rail-xor2" ("dr_xor2" 0 1 2 3 4 5) (1 "dr_xor2"))
("dual-rail-xor2-ncl" ("dr_xor2_ncl" 0 1 2 3 4 5) (1 "dr_xor2_ncl"))
("dual-rail-ao21" ("dr_ao21" 0 1 2 3 4 5 6 7) (1 "dr_ao21"))
("dual-rail-ao21-bal" ("dr_ao21_bal" 0 1 2 3 4 5 6 7) (1 "dr_ao21_bal"))
("dual-rail-ao21-ncl" ("dr_ao21_ncl" 0 1 2 3 4 5 6 7) (1 "dr_ao21_ncl"))
("dual-rail-ineq-comp" ("dr_ineq_comp" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp"))
("dual-rail-ineq-comp-bal" ("dr_ineq_comp_bal" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp_bal"))
("dual-rail-ineq-comp-ncl" ("dr_ineq_comp_ncl" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "dr_ineq_comp_ncl"))
("dual-rail-mux2" ("dr_mux2" 0 1 2 3 4 5 6 7) (1 "dr_mux2"))
("dual-rail-mux2-ncl" ("dr_mux2_ncl" 0 1 2 3 4 5 6 7) (1 "dr_mux2_ncl"))
("dual-rail-half-adder" ("dr_ha" 0 1 2 3 4 5 6 7) (1 "dr_ha"))
("dual-rail-half-adder-bal" ("dr_ha_bal" 0 1 2 3 4 5 6 7) (1 "dr_ha_bal"))
("dual-rail-half-adder-ncl" ("dr_ha_ncl" 0 1 2 3 4 5 6 7) (1 "dr_ha_ncl"))
("dual-rail-full-adder" ("dr_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_fa"))
("dual-rail-full-adder-bal" ("dr_fa_bal" 0 1 2 3 4 5 6 7 8 9) (1 "dr_fa_bal"))
("dual-rail-dims-adder" ("dr_dims_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_dims_fa"))
("dual-rail-ncl-adder" ("dr_ncl_fa" 0 1 2 3 4 5 6 7 8 9) (1 "dr_ncl_fa"))
("dual-rail-full-adder-primed" ("dr_fa_p" 0 1 2 3 4 5 6 7) (1 "dr_fa_p"))
("dual-rail-full-adder-primed-bal" ("dr_fa_p_bal" 0 1 2 3 4 5 6 7) (1 "dr_fa_p_bal"))
("dual-rail-full-adder-primed-ncl" ("dr_fa_p_ncl" 0 1 2 3 4 5 6 7) (1 "dr_fa_p_ncl"))
("dual-rail-dims-subtracter" ("dr_dims_fs" 0 1 2 3 4 5 6 7 8 9) (1 "dr_dims_fs"))
("dual-rail-ncl-subtracter" ("dr_ncl_fs" 0 1 2 3 4 5 6 7 8 9) (1 "dr_ncl_fs"))
("one-of-four-half-adder" ("oof_ha" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ha"))
("one-of-four-dims-carry-adder" ("oof_dims_ca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_ca"))
("one-of-four-ncl-carry-adder" ("oof_ncl_ca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_ca"))
("oof_dims_ca_se" ("oof_dims_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dims_ca_se"))
("one-of-four-dims-carry-adder-overflow" ("oof_ncl_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ncl_ca_se"))
("one-of-four-full-adder" ("oof_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_fa"))
("one-of-four-dims-full-adder" ("oof_dims_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dims_fa"))
("one-of-four-dims-full-adder-overflow" ("oof_dims_fa_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17) (1 "oof_dims_fa_se"))
("one-of-four-dims-subtracter" ("oof_dims_fs" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dims_fs"))
("one-of-four-ncl-full-adder" ("oof_ncl_fa" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_ncl_fa"))
("one-of-four-ncl-full-adder-overflow" ("oof_ncl_fa_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17) (1 "oof_ncl_fa_se"))
("one-of-four-ncl-subtracter" ("oof_ncl_fs" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_ncl_fs"))
("one-of-four-dims-primed-carry-adder" ("oof_dims_pca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_pca"))
("one-of-four-ncl-primed-carry-adder" ("oof_ncl_pca" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_pca"))
("one-of-four-dims-primed-carry-adder-overflow" ("oof_dims_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dims_pca_se"))
("one-of-four-ncl-primed-carry-adder-overflow" ("oof_ncl_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_ncl_pca_se"))
("one-of-four-dual-rail-dims-carry-adder" ("oof_dr_dims_ca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_dims_ca"))
("one-of-four-dual-rail-ncl-carry-adder" ("oof_dr_ncl_ca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_ncl_ca"))
("one-of-four-dual-rail-dims-carry-adder-overflow" ("oof_dr_dims_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_dims_ca_se"))
("one-of-four-dual-rail-ncl-carry-adder-overflow" ("oof_dr_ncl_ca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_ncl_ca_se"))
("one-of-four-dual-rail-dims-primed-carry-adder" ("oof_dr_dims_pca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_dims_pca"))
("one-of-four-dual-rail-ncl-primed-carry-adder" ("oof_dr_ncl_pca" 0 1 2 3 4 5 6 7 8 9 10 11 12 13) (1 "oof_dr_ncl_pca"))
("one-of-four-dual-rail-dims-primed-carry-adder-overflow" ("oof_dr_dims_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_dims_pca_se"))
("one-of-four-dual-rail--ncl-primed-carry-adder-overflow" ("oof_dr_ncl_pca_se" 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (1 "oof_dr_ncl_pca_se"))
("one-of-four-dims-and2" ("oof_dims_and2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_and2"))
("one-of-four-ncl-and2" ("oof_ncl_and2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_and2"))
("one-of-four-dims-or2" ("oof_dims_or2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_or2"))
("one-of-four-ncl-or2" ("oof_ncl_or2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_or2"))
("one-of-four-dims-xor2" ("oof_dims_xor2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_dims_xor2"))
("one-of-four-ncl-xor2" ("oof_ncl_xor2" 0 1 2 3 4 5 6 7 8 9 10 11) (1 "oof_ncl_xor2"))
("oof_dims_equal" ("oof_dims_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_equal"))
("oof_ncl_equal" ("oof_ncl_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_equal"))
("oof_dr_dims_equal" ("oof_dr_dims_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dr_dims_equal"))
("oof_dr_ncl_equal" ("oof_dr_ncl_equal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dr_ncl_equal"))
("one-of-four-dims-inequal" ("oof_dims_inequal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_inequal"))
("one-of-four-ncl-inequal" ("oof_ncl_inequal" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_inequal"))
("oof_dr_dims_inequal" ("oof_dr_dims_inequal" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_inequal"))
("one-of-four-dual-rail-ncl-inequal" ("oof_dr_ncl_inequal" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_inequal"))
("one-of-four-dims-comp" ("oof_dims_comp" 0 1 2 3 4 5 6 7 8 9 10) (1 "oof_dims_comp"))
("one-of-four-ncl-comp" ("oof_ncl_comp" 0 1 2 3 4 5 6 7 8 9 10) (1 "oof_ncl_comp"))
("oof_dr_dims_ineq_comp" ("oof_dr_dims_ineq_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_dims_ineq_comp"))
("oof_dr_ncl_ineq_comp" ("oof_dr_ncl_ineq_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_ncl_ineq_comp"))
("oof_dr_dims_ineq_sgn_comp" ("oof_dr_dims_ineq_sgn_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_dims_ineq_sgn_comp"))
("oof_dr_ncl_ineq_sgn_comp" ("oof_dr_ncl_ineq_sgn_comp" 0 1 2 3 4 5 6 7 8) (1 "oof_dr_ncl_ineq_sgn_comp"))
("one-of-four-dims-less-than" ("oof_dims_lt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_lt"))
("one-of-four-ncl-less-than" ("oof_ncl_lt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_lt"))
("one-of-four-dims-greater-than" ("oof_dims_gt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_dims_gt"))
("one-of-four-ncl-greater-than" ("oof_ncl_gt" 0 1 2 3 4 5 6 7 8 9) (1 "oof_ncl_gt"))
("one-of-four-dual-rail-dims-less-than" ("oof_dr_dims_lt" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_lt"))
("one-of-four-dual-rail-ncl-less-than" ("oof_dr_ncl_lt" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_lt"))
("one-of-four-dual-rail-dims-greater-than" ("oof_dr_dims_gt" 0 1 2 3 4 5 6 7) (1 "oof_dr_dims_gt"))
("one-of-four-dual-rail-ncl-greater-than" ("oof_dr_ncl_gt" 0 1 2 3 4 5 6 7) (1 "oof_dr_ncl_gt"))
("dual-rail-dims-comp" ("dr_dims_comp" 0 1 2 3 4 5 6) (1 "dr_dims_comp"))
("dual-rail-ncl-comp" ("dr_ncl_comp" 0 1 2 3 4 5 6) (1 "dr_ncl_comp"))
("dual-rail-dims-less-than" ("dr_dims_lt" 0 1 2 3 4 5) (1 "dr_dims_lt"))
("dual-rail-ncl-less-than" ("dr_ncl_lt" 0 1 2 3 4 5) (1 "dr_ncl_lt"))
("dual-rail-dims-greater-than" ("dr_dims_gt" 0 1 2 3 4 5) (1 "dr_dims_gt"))
("dual-rail-ncl-greater-than" ("dr_ncl_gt" 0 1 2 3 4 5) (1 "dr_ncl_gt"))
("one-of-three-dual-rail-dims-comp" ("dr_oot_dims_comp" 0 1 2 3 4 5 6) (1 "dr_oot_dims_comp"))
("one-of-three-dual-rail-ncl-comp" ("dr_oot_ncl_comp" 0 1 2 3 4 5 6) (1 "dr_oot_ncl_comp"))
("one-of-three-dims-comp" ("oot_dims_comp" 0 1 2 3 4 5 6 7 8) (1 "oot_dims_comp"))
("one-of-three-ncl-comp" ("oot_ncl_comp" 0 1 2 3 4 5 6 7 8) (1 "oot_ncl_comp"))
("dual-rail-latch" ("dr_latch" 0 1 2 3 4) (1 "dr_latch"))
("dual-rail-spacer-latch" ("dr_spacer_latch" 0 1 2 3 4) (1 "dr_spacer_latch"))
("dual-rail-ncl-latch" ("dr_ncl_latch" 0 1 2 3 4) (1 "dr_ncl_latch"))
("dual-rail-true-ncl-latch" ("dr_tncl_latch" 0 1 2 3 4 5) (1 "dr_tncl_latch"))
("one-of-four-latch" ("oof_latch" 0 1 2 3 4 5 6 7 8) (1 "oof_latch"))
("one-of-four-ncl-latch" ("oof_ncl_latch" 0 1 2 3 4 5 6 7 8) (1 "oof_ncl_latch"))
("one-of-four-true-ncl-reg" ("oof_tncl_latch" 0 1 2 3 4 5 6 7 8 9) (1 "oof_tncl_latch"))
balsa-tech-xilinx/xilinx/drive-table0000644003172000014400000000000010212061546017764 0ustar tomswapt00000000000000balsa-tech-xilinx/xilinx/Makefile.am0000644003172000014400000000052510212061546017713 0ustar tomswapt00000000000000## Process this file with automake to produce Makefile.in
techxilinxdir = $(datadir)/tech/xilinx
techxilinx_DATA = \
balsa-cells.net \
balsa-cells-caps.net \
components.abs \
gate-mappings \
gate-mappings-caps \
drive-table \
xilinx \
xilinx-cells.net \
xilinx-cells-caps.net \
balsa-mgr.cfg
EXTRA_DIST = \
$(techxilinx_DATA)
balsa-tech-xilinx/xilinx/xilinx0000644003172000014400000000225210212061546017114 0ustar tomswapt00000000000000;;;
;;; `xilinx'
;;; Generic Xilinx tech. description
;;;
;;; 2004-06-02, Sam Taylor
;;; 2002-10-15, Andrew Bardsley
;;;
(define purpose (let ((purpose (assoc "cad" breeze-style-options)))
(if purpose (cdr purpose) "cadence")))
(net-signature-for-netlist-format 'verilog #t)
;;; max. no. of inputs for and/or/nand/nor gates and c-elements
(set! tech-gate-max-fan-in 4)
(set! tech-c-element-max-fan-in 3)
(set! tech-map-cell-name (net-simple-cell-name-mapping #f)) ;;; mapping
(set! tech-cell-name-max-length 64)
(if (string=? purpose "cadence")
(begin
(set! tech-gnd-component-name "gnd")
(set! tech-vcc-component-name "vcc")
(set! breeze-gates-net-files '("xilinx-cells" "balsa-cells"))
(set! breeze-gates-mapping-file (string-append breeze-tech-dir "gate-mappings")))
(begin
(set! tech-gnd-component-name "GND")
(set! tech-vcc-component-name "VCC")
(set! breeze-gates-net-files '("xilinx-cells-caps" "balsa-cells-caps"))
(set! breeze-gates-mapping-file (string-append breeze-tech-dir "gate-mappings-caps")))
)
(set! breeze-primitives-file (string-append breeze-tech-dir "components.abs"))
(set! breeze-gates-drive-file (string-append breeze-tech-dir "drive-table"))
balsa-tech-xilinx/xilinx/xilinx-cells-caps.net0000644003172000014400000003421310212061546021727 0ustar tomswapt00000000000000;;;
;;; `xilinx-cells-caps.net'
;;; Xilinx Common Cells
;;;
;;; 02 Jun 2004, Sam Taylor
;;; 21 Jul 1999, Andrew Bardsley
;;;
(circuit "AND2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "AND2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "AND2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "AND3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "AND3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "AND3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "AND3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "AND4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "AND5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "AND5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NAND2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NAND2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NAND3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NAND3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NAND3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NAND3B3" (ports
("o" output 1)("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NAND4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NAND5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NAND5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "OR2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "OR2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "OR3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "OR3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "OR3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "OR3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "OR4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "OR5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "OR5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR1" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "NOR2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NOR2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NOR2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "NOR3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NOR3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NOR3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NOR3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "NOR4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "NOR5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "NOR5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XOR2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XOR2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XOR3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XOR3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XOR3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XOR3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XOR4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XOR5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XOR5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XNOR2B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XNOR2B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "XNOR3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XNOR3B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XNOR3B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XNOR3B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "XNOR4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR4B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR4B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR4B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR4B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "XNOR5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "XNOR5B5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "GND" (ports
("g" output 1)) (nets) (instances))
(circuit "VCC" (ports
("p" output 1)) (nets) (instances))
(circuit "INV" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "BUF" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "FD" (ports ("q" output 1) ("c" input 1) ("d" input 1)) (nets) (instances))
(circuit "FDC" (ports ("q" output 1) ("c" input 1) ("clr" input 1)
("d" input 1)) (nets) (instances))
(circuit "FDCE" (ports ("q" output 1) ("c" input 1) ("ce" input 1) ("clr" input 1)
("d" input 1)) (nets) (instances))
balsa-tech-xilinx/xilinx/components.abs0000644003172000014400000002212010212061546020526 0ustar tomswapt00000000000000;;;
;;; `components.abs'
;;; Breeze primitive components for technology xilinx
;;;
;;; 10 Aug 2001, Andrew Bardsley
;;;
;;; $Id: components.abs,v 1.2 2004/06/02 14:06:11 taylors0 Exp $
;;;
(primitive-part "CallMux"
(parameters
("width" (named-type "cardinal"))
("inputCount" (named-type "cardinal"))
)
(ports
(arrayed-port "inp" passive input (numeric-type #f (param "width")) 0 (param "inputCount"))
(port "out" active output (numeric-type #f (param "width")))
)
(symbol
(centre-string "|")
)
(implementation
(style "four_b_rb"
(nodes
("muxOut" (param "width") 0 1)
("select" 1 0 1)
("nselect" 1 0 1)
("nwaySelect" (param "inputCount") 0 1)
("nwayMuxOut" (param "width") 0 (param "inputCount"))
)
(gates
(case (param "inputCount")
((2)
(cell "set-reset-flip-flop"
(req (bundle "inp" 1))
(req (bundle "inp" 0))
(node "select")
(node "nselect")
)
(and
(combine (ack (each "inp")))
(combine (node "nselect") (node "select"))
(combine (dup 2 (ack "out")))
)
(mux2 (req "out") (req (each "inp")) (node "select"))
(mux2 (data "out") (data (each "inp")) (combine (dup (param "width") (node "select"))))
)
(else
(or (req "out") (req (each "inp")))
(c-element
(combine (ack (each "inp")))
(combine (req (each "inp")))
(combine (dup (param "inputCount") (ack "out")))
)
(or
(node "nwaySelect")
(combine (ack (each "inp")))
(combine (req (each "inp")))
)
(nand
(combine (node (each "nwayMuxOut")))
(combine (data (each "inp")))
(combine (dup-each (param "width") (smash (node "nwaySelect"))))
)
(nand
(data "out")
(node (each "nwayMuxOut"))
)
)
)
)
)
(style "dual_b" (include tech "common" "data-dual/CallMux"))
(style "one_of_2_4" (include tech "common" "data-1of4/CallMux"))
)
)
(primitive-part "Variable"
(parameters
("width" (named-type "cardinal"))
("readPortCount" (named-type "cardinal"))
("name" (string) not-used)
)
(ports
(port "write" passive input (numeric-type #f (param "width")))
(arrayed-port "read" passive output (numeric-type #f (param "width")) 0 (param "readPortCount"))
)
(symbol
(centre-string (param "name"))
)
(implementation
(style "four_b_rb"
(nodes
("nWrite" 1 0 1)
)
(gates
(inv (node "nWrite") (req "write"))
(inv (ack "write") (node "nWrite"))
(latch (combine (dup (param "width") (node "nWrite"))) (data "write") (data (bundle "read" 0)))
)
(connections
(connect (combine (req (each "read"))) (combine (ack (each "read"))))
(if (>= (param "readPortCount") 2)
(connect (data (bundle "read" 0)) (data (bundles "read" 1 (- (param "readPortCount") 1))))
)
)
)
(style "dual_b"
(nodes
("qt" (param "width") 0 1)
("qf" (param "width") 0 1)
("wackt" (param "width") 0 1)
("wackf" (param "width") 0 1)
("wack" (param "width") 0 1)
("one" 1 0 1)
)
(gates
(vcc (node "one"))
; Flipflop: use a DFF with clear (xilinx FDC component)
(cell "edge-dff-clr"
(req1 "write") (combine (dup (param "width") (node "one")) )
(req0 "write") (node "qt")
)
; invert Q outputs
(inv (node "qf") (node "qt"))
; write ack signal generation
(nand (node "wackt") (req1 "write") (node "qt"))
(nand (node "wackf") (req0 "write") (node "qf"))
(nand (node "wack") (node "wackt") (node "wackf"))
(c-element (ack "write") (smash (node "wack")))
; Read ports
(and
(combine (ack1 (each "read")))
(combine (dup-each (param "width") (req (each "read"))))
(combine (dup (param "readPortCount") (node "qt")))
)
(and
(combine (ack0 (each "read")))
(combine (dup-each (param "width") (req (each "read"))))
(combine (dup (param "readPortCount") (node "qf")))
)
)
(connections
)
)
(style "one_of_2_4"
(defines
(width-odd (quotient (+ (param "width") 1) 2))
(width-even (quotient (param "width") 2))
(plural (> (param "width") 1)) ;; more than one
(odd (= (modulo (param "width") 2) 1))
)
(nodes
("store0" width-odd 0 1)
("store1" width-odd 0 1)
("store2" width-even 0 1)
("store3" width-even 0 1)
("orcomp" width-even 0 1)
("oddcomp" 1 0 1)
)
(gates
(if plural
(gates
(or (node "orcomp")
(slice 0 width-even (req0 "write"))(slice 0 width-even (req1 "write"))
(slice 0 width-even (req2 "write"))(slice 0 width-even (req3 "write")))
)
) ;; completion of input
(if odd
(gates
(or (node "oddcomp") (slice width-even 1 (req0 "write"))(slice width-even 1 (req1 "write")))
)
)
(if plural ;; producing ack to latch writes
(gates
(if odd
(c-element (ack "write") (smash (node "orcomp")) (node "oddcomp"))
(c-element (ack "write") (smash (node "orcomp")))
)
)
(connect (node "oddcomp") (ack "write"))
)
(if plural
(gates
(latch (combine (dup width-even (ack "write"))) (slice 0 width-even (req0 "write")) (slice 0 width-even (node "store0")))
(latch (combine (dup width-even (ack "write"))) (slice 0 width-even (req1 "write")) (slice 0 width-even (node "store1")))
(latch (combine (dup width-even (ack "write"))) (slice 0 width-even (req2 "write")) (slice 0 width-even (node "store2"))) ;; slicing maybe unnecessary
(latch (combine (dup width-even (ack "write"))) (slice 0 width-even (req3 "write")) (slice 0 width-even (node "store3")))
)
)
(if odd
(gates
(latch (ack "write") (slice width-even 1 (req0 "write")) (slice width-even 1 (node "store0")))
(latch (ack "write") (slice width-even 1 (req1 "write")) (slice width-even 1 (node "store1")))
)
)
; Read ports
(and (combine (ack0 (each "read"))) (combine (dup-each width-odd (req (each "read"))))
(combine (dup (param "readPortCount") (node "store0"))))
(and (combine (ack1 (each "read"))) (combine (dup-each width-odd (req (each "read"))))
(combine (dup (param "readPortCount") (node "store1"))))
(if plural
(gates
(and (combine (ack2 (each "read"))) (combine (dup-each width-even (req (each "read"))))
(combine (dup (param "readPortCount") (node "store2"))))
(and (combine (ack3 (each "read"))) (combine (dup-each width-even (req (each "read"))))
(combine (dup (param "readPortCount") (node "store3"))))
)
)
)
(connections)
)
)
)
(primitive-part "Arbiter" ; FIXME
(parameters
)
(ports
(sync-port "inpA" passive)
(sync-port "inpB" passive)
(sync-port "outA" active)
(sync-port "outB" active)
)
(symbol
(centre-string "(>")
)
(implementation
(style "four_b_rb"
(nodes
("miA" 1 0 1)
("miB" 1 0 1)
("moA" 1 0 1)
("moB" 1 0 1)
)
(gates
(mutex (node "miA") (node "miB") (node "moA") (node "moB"))
(or (node "miA") (req "inpA") (ack "outA"))
(or (node "miB") (req "inpB") (ack "outB"))
(and (req "outA") (node "moA") (req "inpA"))
(and (req "outB") (node "moB") (req "inpB"))
(connect (ack "outA") (ack "inpA"))
(connect (ack "outB") (ack "inpB"))
)
)
(style "dual_b" (include tech "common" "ctrl-broad/Arbiter"))
(style "one_of_2_4" (include tech "common" "ctrl-broad/Arbiter"))
)
)
(primitive-part "CaseFetch"
(parameters
("width" (named-type "cardinal"))
("indexWidth" (named-type "cardinal"))
("inputCount" (named-type "cardinal"))
("specification" (string))
)
(ports
(port "out" passive output (numeric-type #f (param "width")))
(port "index" active input (numeric-type #f (param "indexWidth")))
(arrayed-port "inp" active input (numeric-type #f (param "width")) 0 (param "inputCount"))
)
(symbol
(centre-string "@T" (param "specification"))
)
(implementation
(style "four_b_rb"
(nodes
("t" (param "indexWidth") 0 1)
("c" (param "indexWidth") 0 1)
("outputreq" 1 0 1)
("latchedIndex" (param "indexWidth") 0 1)
("muxOut" (param "width") 0 (param "inputCount"))
("elseAck" 1 0 1)
)
(gates
(s-element (req "out") (node "outputreq") (req "index") (ack "index"))
(latch (combine (dup (param "indexWidth") (req "index"))) (data "index") (node "latchedIndex"))
(demux2 (combine (dup (param "indexWidth") (node "outputreq"))) (node "c") (node "t") (node "latchedIndex"))
(if (complete-encoding? (param "specification") (param "indexWidth"))
(gates
(decode and-or (param "specification") (node "c") (node "t") (req (each "inp")))
(or (ack "out") (ack (each "inp")))
)
(gates
(decode and-or (param "specification") (node "c") (node "t") (req (each "inp")) (node "elseAck"))
(or (ack "out") (ack (each "inp")) (node "elseAck"))
)
)
(nand
(combine (node (each "muxOut")))
(combine (dup-each (param "width") (ack (each "inp"))))
(combine (data (each "inp")))
)
(nand
(data "out")
(node (each "muxOut"))
)
)
)
(style "dual_b" (include tech "common" "data-dual/CaseFetch"))
(style "one_of_2_4" (include tech "common" "data-1of4/CaseFetch"))
)
)
(include tech "common" ".." "components")
balsa-tech-xilinx/xilinx/xilinx-cells.net0000644003172000014400000003420710212061546021006 0ustar tomswapt00000000000000;;;
;;; `xilinx-cells.net'
;;; Xilinx Common Cells
;;;
;;; 02 Jun 2004, Sam Taylor
;;; 21 Jul 1999, Andrew Bardsley
;;;
(circuit "and2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "and2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "and2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "and3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "and3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "and3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "and3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "and4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "and5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "and5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nand2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nand2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nand3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nand3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nand3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nand3b3" (ports
("o" output 1)("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nand4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nand5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nand5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "or2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "or2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "or3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "or3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "or3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "or3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "or4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "or5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "or5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor1" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "nor2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nor2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nor2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "nor3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nor3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nor3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nor3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "nor4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "nor5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "nor5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xor2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xor2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xor3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xor3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xor3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xor3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xor4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xor5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xor5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xnor2b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xnor2b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)) (nets) (instances))
(circuit "xnor3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xnor3b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xnor3b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xnor3b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1)
("i2" input 1)) (nets) (instances))
(circuit "xnor4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor4b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor4b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor4b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor4b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1)) (nets) (instances))
(circuit "xnor5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b1" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b2" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b3" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b4" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "xnor5b5" (ports
("o" output 1) ("i0" input 1) ("i1" input 1) ("i2" input 1)
("i3" input 1) ("i4" input 1)) (nets) (instances))
(circuit "gnd" (ports
("g" output 1)) (nets) (instances))
(circuit "vcc" (ports
("p" output 1)) (nets) (instances))
(circuit "inv" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "buff" (ports
("o" output 1) ("i" input 1)) (nets) (instances))
(circuit "fd" (ports ("q" output 1) ("c" input 1) ("d" input 1)) (nets) (instances))
(circuit "fdc" (ports ("q" output 1) ("c" input 1) ("clr" input 1)
("d" input 1)) (nets) (instances))
(circuit "fdce" (ports ("q" output 1) ("c" input 1) ("ce" input 1) ("clr" input 1)
("d" input 1)) (nets) (instances))
balsa-tech-xilinx/INSTALL0000644003172000014400000000046710212064452015401 0ustar tomswapt00000000000000 |_ _ | _ _ |_ _ _ |_ _ _.|.._ _ _ [ Balsa system Xilinx technology ]
|_)(_\|_/ (_\ - |_(-'(_.| | - _/_|||| |_/_ For Balsa version 3
(C) 2005 AMULET Group, Dept. of Computer Science,
The University of Manchester,
Manchester
M13 9PL, UK
balsa-tech-xilinx/COPYING0000644003172000014400000000006410212061616015373 0ustar tomswapt00000000000000(C) 2000 AMULET Group, The University of Manchester
balsa-tech-xilinx/ChangeLog0000644003172000014400000000003010212061616016103 0ustar tomswapt0000000000000020020403: first version
balsa-tech-xilinx/bootstrap0000755003172000014400000000015010212061616016277 0ustar tomswapt00000000000000#! /bin/sh
set -x
aclocal
# libtoolize --force --copy
autoheader
automake --add-missing --copy
autoconf
balsa-tech-xilinx/mkinstalldirs0000755003172000014400000000132710212061616017151 0ustar tomswapt00000000000000#! /bin/sh
# mkinstalldirs --- make directory hierarchy
# Author: Noah Friedman
# Created: 1993-05-16
# Public domain
# $Id: mkinstalldirs,v 1.1.1.1 2002/04/03 15:16:41 tomsw Exp $
errstatus=0
for file
do
set fnord `echo ":$file" | sed -ne 's/^:\//#/;s/^://;s/\// /g;s/^#/\//;p'`
shift
pathcomp=
for d
do
pathcomp="$pathcomp$d"
case "$pathcomp" in
-* ) pathcomp=./$pathcomp ;;
esac
if test ! -d "$pathcomp"; then
echo "mkdir $pathcomp"
mkdir "$pathcomp" || lasterr=$?
if test ! -d "$pathcomp"; then
errstatus=$lasterr
fi
fi
pathcomp="$pathcomp/"
done
done
exit $errstatus
# mkinstalldirs ends here