The AMULET3 microprocessor


AMULET3 will be the third generation asynchronous ARM processor. Its predecessors, AMULET1 and AMULET2e, have been fabricated and are described elsewhere.

In designing AMULET3 there is a slightly different design philosophy from the earlier devices; these were primarily designed as low power processors and performance was a secondary consideration. AMULET3 will attempt to retain the high power efficiency of the earlier devices whilst yielding much higher performance. Although we do not expect performance as high as StrongARM (as has been reported elsewhere) we do expect to close the gap between asynchronous and synchronous ARMs significantly. AMULET devices are designed in the same non-process specific techology that ARM Ltd. use; a fair basis for camparison will therefore be ARM9.

AMULET3 has been modelled in LARD an asynchronous hardware design language developed within the AMULET group. This has - and is - providing useful information on the effect of alterations in the microarchitecture of the processor.

The bus structure will be more like StrongARM than previous AMULET processors. For example the register bank has been extended to allow up to three simultaneous reads and a method for forwarding results with a minimal penalty within the asynchronous environment has been devised [REF].

Features (will probably) include:

There is also increasing evidence that asynchronous circuits emit less intense and non-harmonic EMI; AMULET3's EMC properties should therefore be better than an equivalent synchronous device.

This page is still developing.
Watch this space for further developments!


Could you use it?

If you have an application which requires significant computing power, low power dissipation and low EM emissions - and you're prepared to take it to silicon - why not talk to us?


The AMULET3 development is supported by the OMI/ATOM project. The designers wish to acknowledge this support from the CEC.