From nowick@cs.columbia.edu Wed Nov 30 01:40:42 1994 Date: Tue, 29 Nov 94 20:34:06 EST From: Steven Nowick To: asynchronous-private@cs.columbia.edu Subject: [Luciano Lavagno : Re: Question concerning delay hazards] Cc: nowick@cs.columbia.edu Content-Length: 2068 X-Lines: 41 Status: RO Date: Mon, 28 Nov 1994 17:03:32 -0800 From: Luciano Lavagno Content-Type: text Content-Length: 1944 jeroen@es.ele.tue.nl (Jeroen Rutten) writes: [....] > I do agree that there are a lot of methods which assume Input-Output mode. Many > claim to be Speed Independent, Quasi-Delay Insensitive, or even Delay > Insensitive. A lot of these methods however make severe assumptions in the > implementation phase. They merge gates into complex ones and declare them > atomic, or they suffer from an overhead penalty of at least 100 % because they > use dual-rail encoding. Now your point is more clear... > My question was intended to find out if there exist methods assuming > Input-Output mode which use conventional two-level logic / multi-level logic and > which can take into account delay hazards. At this point, I can give a detailed answer about my proposed solution to the problem. I hope somebody else will also accept the challenge and describe his/her own solution (I am specifically referring to the Stanford and to the Aizu groups here). My proposal is to use an STG specification (i.e., use I/O mode), come up with a logic implementation using ANY available library (e.g. your favorite standard cells) and then do delay padding to make it work in "local fundamental mode". This means that every node (== logic gate, rather than a complete circuit, as in the classical theory) is given enough time to settle. All this is described more in detail in my thesis, and is implemented in SIS, the sequential logic syntehsis syetem freely distributed by U.C. Berkeley. If you want I can give you more detailed pointers in private (I don't want to use the mailing list as an advertising medium :-) ). Ciao ! Luciano -- Luciano Lavagno +39-11-564-4150 (fax 4099) lavagno@polito.it Dip. di Elettronica, Politecnico, C. Duca degli Abruzzi 24, 10129 Torino, ITALY till December 5: +1-408-428-5326 (fax +1-510-486-0205) luciano@cadence.com Cadence Berkeley Labs, 1919 Addison St. #303-304, Berkeley - CA 94704-1144