What is SIS ?


From: Luciano Lavagno (lavagno@polv2k.polito.it)
SIS is available through anonymous FTP from here (ic.eecs.berkeley.edu/pub/Sis)
SIS, the UCB sequential synthesis system, that offers asynchronous synthesis as well as synchronous sequential and combinational multi-level logic synthesis capabilities. Its asynchronous package was developed by myself, Cho Moon and Paul Stephan, so we can also provide assistance in bug fixing and so on. It is written in C, and has been ported to most workstations (DEC, SUN, IBM) without problems. It is available with source code.
The specification formalism, Chu's Signal Transition Graph, is similar to timing diagrams: the user defines which transitions cause which transitions. E.g. a rising transition on the set input of a set-reset flip-flop causes a rising transition on the Q output, this causes a falling transition on the QBAR output, and so on.
More formally, the STG is an interpreted Petri net. An FSM-style input will also be provided for users who prefer it (even though it allows less optimizations, and hence it is discouraged).
It uses two different delay models for synthesis, one where the logic is assumed to be implemented as two-level logic gates with no bounds on the amount of delays of each gate, and one where each gate and wire has a bounded delay (given by the implementation library description).
The system can perform the following operations:
We have a set of papers and a sort of user's manual that leads you through a set of examples of how to use the system.
Contact: Luciano Lavagno (lavagno@polv2k.polito.it)
Note: There are two "versions" of SIS. Contact for the "supported" one is: sis@ic.berkeley.edu (for "registration" purposes, so that you can be notified when there is an upgrade).