SYN 2.01, Synthesis of speed-independent circuits

From: Peter Beerel (
SPECIFICATION: State Graph specification description which satisfies complete state coding (CSC) and is distributive with input choice.
IMPLEMENTATION: DELAY MODEL: Unbounded gate delay model
BASIC GATES USED: ANDs, ORs, C_Elements with unlimited fanin and possible attached input inverters.
I have modified a version of SIS to generate the low-level state graph from an STG. I have also written a converter from extended burst-mode FSMs (, to state graphs with semi-automated state variable insertion. Both are available upon request.
EXTENSIONS: SYN 3.0 soon to be available (hopefully): Synthesis with basic gates with limited fanin.
AVAILABILITY: SYN 2.01 can be obtained through anonymous FTP from here ( Associated papers (TAU '92 and ICCAD '92) are also FTPable.
CONTACT: Peter A. Beerel, (, AEL 007,Stanford University, Stanford, CA 94305, (415)-723-9510