Pest

The results produced are only an estimate and even though the results a presented in terms of Joules, the actual numbers should be treated with a pinch of salt since there are a number of inaccuracies in the calculations used. Nevertheless, the results do make it clear which are the most energy consuming sections of a circuit and can be used to give a rough feel for the total energy consumption. If you require more accurate power analyses and you have the money, the producers of TimeMill® have a companion tool called PowerMill.

Usage

           pest  tracefile [capfile]

tracefile

The name of the design unit you wish to process. The name may include the .out extension for the trace file, but the .out extensions is assumed if it is not given. This filename may be used to derive the name of the capacitance file.

capfile

The name of the file that contains the capacitance at each node (as produced by TimeMill®). The name may include the .cap extension for this file, but that will be assumed if it is not explicitly included. If this optional argument is not given on the command line the capacitance information is searched for in tracefile.cap. The capacitances are assumed to be measured in femtofarads.

Output Files

The output produced by the tool should be self explanatory, but can be very long winded since it lists the energy consumption for every node. To avoid having to read the whole file, the most important information is placed at the start of the file, starting with the total energy consumption, followed by the list of the energy consumed at each node, sorted in descending order of consumption.

Detailed behaviour

This calculation is based on the dynamic power consumption which is the largest factor in the total power consumption for CMOS circuits. It ignores the static leakage current and the crowbar current that flows through the transistor stack during the short time that both the P and N transistors are active. It has been suggested that these sources of power consumption account for 10-20% of the total power, so the tool may be expected to produce an under estimate of the power consumption.

Other inaccuracies also creep into the estimate:

• The first transition on every node is ignored, since this is assumed to be a statement of the initialisation state of that node, and this power model is intended for use in measuring a running circuit, not the start-up costs.

• The calculation is dependent on the accuracy of the capacitance figures passed to the tool.

• Precise information about the actual voltage swing for a transition is not available, so the tool assumes that all transitions cover the full 0V to VDD range. The value of VDD is automatically extracted from the .out file. This full swing assumption is not unreasonable for CMOS circuits, where most signals will involve full range transitions. In practice, however, some signals will not show a full range transition, so the tool will produce an overestimate of the dynamic power consumption.

  The information about signals that is actually available to the tool indicates when the voltage crosses the low and high logic thresholds in place for the given simulation. Therefore the alternative to assuming VDD swings would be to base the calculation on the difference between the two logic thresholds, but that would be likely to produce a considerable underestimate.

• The tool only considers full transitions between the two logic thresholds. A signal might, for example, start at logic 0 move up to an undefined state, then be driven back to 0. Those voltage changes would result in power consumption, but they will be ignored by the tool.

Implementation Language

Copyright and licence

Source Code