Parallel Structures for Asynchronous Microprocessors
Philip B. Endecott
Abstract
This paper considers the implementation of pipelining and superscalar
parallelism in asynchronous processors. The performance of simple
pipelines and superscalar structures is improved by asynchronous
implementation. The organisation of general purpose processors is more
complex: they include forwarding paths joining non-adjacent pipeline
stages. Unfortunately the additional synchronisation required by
forwarding paths is detrimental to performance, yet not having
forwarding is also detrimental. A solution called conditional
forwarding is proposed but it is found that conventional instruction
sets do not permit conditional forwarding. To allow this technique to
be used an alternative programming model called explicit forwarding is
introduced. In a processor with explicit forwarding the destination
to which the result of an instruction must be sent is indicated
explicitly by the instruction; in contrast in a conventional
instruction set the routing of the result of an instruction is deduced
from the register specifiers of adjacent instructions. The paper
concludes by describing an experimental processor called SCALP
(Superscalar Asynchronous Low-Power Processor) which uses explicit
forwarding.
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