Differential register bank design for self timed differential bipolar technology
Jackson D.L., Kelly R. and Brackenbury L.E.M.
Abstract
A high performance differential bipolar datapath, based on the ARM
architecture has been designed using `micropipeline' self timed
techniques. The datapath design included a full-custom 31x32 bit Register
Bank. Traditional bipolar single-ended design techniques are not suited to
implementing a RAM of this size on the target technology. This has led to
the adoption of a fully differential circuit for the RAM cell here. This
paper describes the challenges of designing such a differential Register
Bank and the surrounding self timed control. The data path has been
fabricated by GEC Plessey Semiconductors and is fully operational. Results
for the Register Bank are presented in terms of speed, power consumption
and area.