Utilising Dynamic Logic for Low Power Consumption in Asynchronous
Circuits
Craig Farnsworth, Doug Edwards and Shiv Sikand
Abstract
Dynamic logic offers compact, fast solutions for synchronous
design. Asynchronous design methodologies which conform to the
bounded-delay model can also utilize dynamic logic for combinational
circuits obtaining similar benefits to the synchronous case. To achieve
these benefits, the logic is held in precharge until it is required and the
evaluation phase is completed during a handshake communication action. The
resultant power consumption is low since the input capacitance is far
smaller than equivalent static CMOS circuits and spurious transitions in
the computation are removed.
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