A Micropipelined ARM
S. B. Furber, P. Day, J. D. Garside, N. C. Paver and J. V. Woods
Abstract
An asynchronous implementation of the ARM microprocessor is described. The
design is based on Sutherland's Micropipelines, and allows considerable
internal asynchronous concurrency. The rationale for the work is presented,
the organisation of the chip described, and the characteristics of the chip
described. The design displays unusual properties such as non-deterministic
(but bounded) prefetch depth beyond a branch instruction. This work
demonstrates the feasibility of building complex asynchronous systems and
gives an indication of the costs and benefits of the Micropipeline
approach.
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