One implementation technique which may lead to lower power consumption is the use of asynchronous logic. In particular, asynchronous logic can be more power-efficient in a system with a rapidly-changing computational load. Because of the differences between synchronous and asynchronous logic, certain architectural features are more suited to asynchronous implementation than others. This thesis proposes a number of features that are more suitable for asynchronous implementation. Important areas include the branch mechanism and the way in which data dependencies are dealt with.
Other architectural factors that influence power consumption are investigated. Increasing code density will lead to increased power efficiency because the power consumed in many parts of the computer system is proportional to the rate of instruction fetch. Code density is investigated and ways in which the density of the SPARC architecture could be increased are proposed. The most important improvements are found to result from using a Huffman encoded opcode field and reducing the length of some immediate fields. Other factors are the use of 2-address instructions, load and store multiple instructions and explicit last result re-use. It is also noted that the power efficiency of the memory system can be increased through the use of multiple level caches and by using a copy-back write policy.
By combining these features, an architecture with a power efficiency double that of a conventional processor could be constructed.