## Arithmetic and Control Components for an Asynchronous System

Jianwei Liu
### Abstract

This thesis describes arithmetic components (an adder and a multiplier) and
control components which have been designed and implemented for AMULET3i, a
commercial asynchronous embedded system chip incorporating the third
generation asynchronous ARM processor (AMULET3).
A novel carry arbitration scheme is proposed (and has been patented) for
parallel adder circuits. This new scheme provides an efficient encoding in
which the carry is generated by arbitrating several input carry requests,
exploiting the associativity of the carry computation. Post-layout
simulation, in a 0.35 micron triple metal CMOS technology, shows that the
adder for AMULET3i takes 1.8 ns to complete the computation of a 32-bit
addition.

The multiplier design uses the modified Booth's algorithm integrated with a
new encoding technique for adjusting the product result of an unsigned
number multiplication. An adjustment value is made on the least significant
32-bit positions. Post-layout simulation, in a 0.35 micron triple metal
CMOS technology, shows that the multiplier for AMULET3i takes 11.2 ns (2.8
ns x 4 cycles) to complete the computation of a 32-bit long
multiplication in the worst case.

Organizing these arithmetic components efficiently into a four-phase
asynchronous pipeline is investigated and a set of speed-independent latch
control circuits is then proposed. Additionally, a set of control modules
for four-phase micropipelines is presented. These two sets of control
components can be used to construct complex and powerful asynchronous
systems.

The thesis is available in postscript form by
ftp
(867kB - gzipped).