An asynchronous methodology may provide solutions to these short-comings by not requiring the distribution of a global clock signal. Instead circuits are constructed from small, self-timed sub-circuits within which temporal dependencies are maintained. Larger, pipelined circuits are constructed by joining these sub-components together using a simple communication protocol. This arrangement allows asynchronous pipelines to have a flexible depth and a data dependent throughput.
A block level simulator has been written that models microprocessor caches developed using a particular asynchronous methodology micropipelines. This thesis describes the development of such caches. It notes the effects of varying various cache parameters and using different strategies whilst attempting to optimise performance for a specific architecture. The target architecture is a micropipelined version of the ARM microprocessor which is currently being developed within the AMULET research group.