The Manchester AsynchRonous Bus for Low Energy is a system level STAMINA bus that is used in the AMULET3i asynchronous system. Features include
  • Zero Quiescent power due to asynchronous operation
  • Processor Independent
  • Full support for burst and atomic transfers
  • 4-Phase micropipeline implementation
  • Centralized arbitration and address decode
  • 8/16/32-bit data transfers.
  • Pipelining of arbitration, address and data cycles of consecutive bus transfers
  • Full support for deferred start/deferred completion/hardware retry to facilitate slow targets and bridging
  • Aborts/software retry support for simple MMU-free systems and bus error handling.
  • Spatial locality optimization support for improved system performance
  • VLSI Test support
  • Tristate or Gated-OR signalling
  • MARBLE is a STAMINA bus with the following parameters:
    Address Channel32 bits
    Data Channel32 bits
    Response Channel1-bit merged with the data channel
    No. of Colours (=outstanding addresses)1
    The MARBLE system used in AMULET3i is shown below. This figure illustrates the features listed above and shows how Harvard Architecture cores, (possibly with local RAM/ROM) can be supported under STAMINA.

    Interface Specifications

    Device-Interface Bundles

    All bundles operate using the 4-phase broad push protocol unless stated otherwise

    Address to bus Bundle

  • Address[31:0]
  • Size[1:0]
  • Prot[1:0]
  • PRED
  • SEQ
  • RNW
  • Lock - make the next transfer atomic with this one
  • In addition, the following signal is available on the fast initiator interface, timing to be arranged:
  • Fast
  • Address from bus

  • Address[31:0]
  • Size[1:0]
  • Prot[1:0]
  • PRED
  • SEQ
  • RNW - read Not write
  • Same -same initiator as last previously
  • Data to bus Bundle

  • D[31:0]
  • Data from bus Bundle

  • D[31:0]
  • Abort Response to bus

  • ABT
  • Abort Response from bus

  • ABT
  • Available for download:

  • ASYNC98 Powerpoiint presentation
  • ASYNC98 Powerpoint slides and notes