Curriculum Vitae

Updated since Oct. 3, 1996, 14:00

Personal Record

Full Name

Oleg (1st name), Alexandrovich (patronymic), Petlin (surname)

Date of Birth

26th of May, 1966 (Kiev, Ukraine)

Marital status

Single

Education

Sept. 1973 - July 1983: Kiev High School no.157 (Ukraine)

Sept. 1983 - June 1989: Kiev Polytechnical Institute (undergraduate)

Nov. 1989 - Nov. 1992: Kiev Polytechnical Institute (postgraduate).

Apr. 1993 - Apr. 1996: University of Manchester, Department of Computer Science (PhD student)

Qualifications

1989: Diploma of System Engineer with Honors in Computer Science (Kiev,Ukraine)

1993: Candidate of Technical Sciences Degree in Computer Science (Kiev,Ukraine)

1994: Master of Science in Computer Science (Manchester, England)

1996: PhD in Computer Science (Manchester, England)

Awards

The Heaviside Premium Award

Awarded in October, 1996, by the Institution of Electrical Engineers (IEE), London, UK, for the best paper of 1995.

Previous Employment

Aug. 1989 - Oct. 1989: Research engineer, Department of Computer Science, Kiev Polytechnical Institute, Ukraine.

Worked as an engineer in the VLSI testing group. Responsibilities: developing methods and techniques for testing of synchronous VLSI circuits using random test patterns.

Teaching

Teaching duties

Oct. 1992 - Mar. 1993: Lecturer, Department of Special Purpose Computers, Kiev Polytechnical Institute, Ukraine.

Worked as a full-time lecturer. Lecture course: "The theory of probabilities and mathematical statistics".

Practice courses:

Demonstration work

Oct. 1993 - May 1994: Demonstrator in Hardware Design labs (1st year labs), "Introduction to Computer Hardware" (CS120), Department of Computer Science, University of Manchester.

Oct. 1994 - May 1996: Demonstrator in Hardware Design labs (2nd year labs), "Digital Circuits and Digital Design" (CS221) and "Digital Signal Processing and ASICs" (CS223), Department of Computer Science, University of Manchester.

Current Employment

July 1996 - present: Research Associate, Department of Computer Science, University of Manchester, Manchester, M13 9PL, UK

Responsibilities: Developing of efficient asynchronous cache architectures for the AMULET3 microprocessor to be used in deeply embedded systems. The project is funded by the EC.

Publications

Conference papers

  1. A.M.Romankevich, V.V.Groll, O.A.Petlin, "A method of designing combinational circuits for random pattern testability", Proc. republ. scien.-tech. conf., Zhitomir, Ukraine, Sept. 17-19, 1991, pp.15-16. (Russian)
  2. A.M.Romankevich, V.V.Groll, O.A.Petlin, "A method of simplifying a test procedure of multi-output counters", Proc. republ. scien.-tech. conf., Shatsk, Ukraine, Sept. 11-14, 1991, p.31. (Russian)
  3. A.M.Romankevich, V.V.Groll, O.A.Petlin, E.V.Nedosekov, "A method of designing digital circuits for random pattern testability", Proc. republ. scien.-tech. conf., Vinnitsa, Ukraine, Nov. 13-15, 1990, part 1, p.6. (Russian)
  4. A.M.Romankevich, V.V.Groll, O.A.Petlin, "On pseudorandom testing testable digital automatons", Proc. republ. scien.-tech. school-seminar, Kamenets-Podolsky, Ukraine, June 19-22, 1990, p.10. (Russian)
  5. O.A.Petlin, S.B.Furber, A.M.Romankevich, V.V.Groll, "Designing asynchronous sequential circuits for random pattern testability", Proc. ACiD-WG Workshop on Testing and Design for Testability (Handouts), INESC-Aveiro, Aveiro, Portugal, Sept. 26-27, 1994. (English)
  6. O.A.Petlin, S.B.Furber, "Scan testing of asynchronous sequential circuits", Proc. 5th Great Lakes Symp. on VLSI, Buffalo, N.Y., USA, Mar. 16-18, 1995, pp. 224-229. (English)
  7. O.A.Petlin, S.B.Furber, "Scan testing of micropipelines", Proc. 13th IEEE VLSI Test Symposium, Princeton, New Jersey, USA, May 1-3, 1995, pp. 296-301. (English)
  8. O. A. Petlin, C. Farnsworth, S. B. Furber, "Design for testability of an asynchronous adder", Proc. of IEE Colloquium on Design and Test of Asynchronous Systems, London, UK, 28 Feb., 1996, pp. 5/1- 5/9. (English)
  9. O.A.Petlin, C.Farnsworth, S.B.Furber, "The built-in self test design of an asynchronous block sorter", submitted to Euro-DAC'96, Geneva, Switzerland, Sept. 1996. (English)
  10. O.A.Petlin, S.B.Furber, "Built-in self-testing of micropipelines", submitted to ICCD'96, Taxes, USA, Oct. 7-9, 1996. (English)
  11. O.A.Petlin, S.B.Furber, "Testing of four-phase micropipelines", to be submitted to the 2nd IEEE International On-Line Testing Workshop, France, July 8-10, 1996. (English)
  12. O.A.Petlin, S.B.Furber, A.M.Romankevich, V.V.Groll, "Designing of handshake sequential machines for random pattern testability", to be submitted to the 5th Asian Test Symposium ATS-96, Taiwan, Nov. 20-22, 1996. (English)

Papers

  1. A.M.Romankevich, V.V.Groll, O.A.Petlin, L.Ph.Karachun, "Structural problems of generating some types of test sequences", Publ. by Ukrainian Institute of Technical Information (Kiev), 15.12.89, No. 2946-Uk89, 12 p. (Russian)
  2. A.M.Romankevich, V.V.Groll, O.A.Petlin, L.Ph.Karachun, "Some questions of the pseudorandom testing of digital circuits", Journal of Kiev Polytechnical Institute, Part: Automation and Electronics, 1990, Issue 27, pp.47-51. (Russian)
  3. A.M.Romankevich, V.V.Groll, O.A.Petlin, "On estimating the length of working cycle of random pattern test generators", Publ. by Ukrainian Institute of Technical Information (Kiev), 23.04.91, N 534-Uk91, 14 p. (Russian)
  4. A.M.Romankevich, V.V.Groll, O.A.Petlin, "Estimating the time of pseudoexhaustive testing of digital circuits", Publ. by Ukrainian Institute of Technical Information (Kiev), 13.03.91, N 329-Uk91, 13 p. (Russian)
  5. A.M.Romankevich, O.A.Petlin, V.V.Groll, M.G.Lukashevich, "On designing testable combinational circuits using multiplexers", Journal of Kiev Polytechnical Institute, Part: Automation and Electronics, 1993, Issue 30, pp. 122-125. (Russian)
  6. O.A.Petlin, M.G.Lukashevich, V.V.Groll, "A technique of designing testable carry chain adders", Journal of Kiev Polytechnical Institute, Part: Automation and Electronics, 1993, Issue 30, pp. 100-103. (Russian)
  7. O.A.Petlin, S.B.Furber, A.M.Romankevich, V.V.Groll, "Designing asynchronous sequential circuits for random pattern testability", IEE Proc.-Comput. Digit. Tech., Vol. 142, No. 4, July 1995. (English)
  8. O.A.Petlin, S.B.Furber, "Power consumption and testability of CMOS VLSI circuits", submitted to IEEE Transactions on CAD (English)
  9. O.A.Petlin, S.B.Furber, "Detecting fabrication faults in C-elements", submitted to IEEE Journal on VLSI Systems (English)

Theses

  1. O.A.Petlin, "Designing of VLSI circuits for random pattern testability", Candidate of Technical Sciences Thesis, Department of Special Purpose Computers, Kiev Polytechnical Institute, Ukraine, February 1993. (Russian)
  2. O.A.Petlin, "Random testing of asynchronous VLSI circuits", M.Sc. Thesis, Department of Computer Science, University of Manchester, October, 1994. (English)
  3. O.A.Petlin, "Design for testability of asynchronous VLSI circuits", Ph.D. Thesis, Department of Computer Science, University of Manchester, submitted in January, 1996. (English)

Technical reports

  1. A.M.Romankevich, V.V.Groll, O.A.Petlin, "Investigation and design of hardware for testing VLSI circuits. Designing digital circuits for random pattern testability", Third Year Project Report, Department of Computer Science, Kiev Polytechnical Institute (Ukraine), 1990.
  2. O.A.Petlin, S.B.Furber, "Designing C-elements for testability", Technical Report UMCS-95-10-2, Department of Computer Science, University of Manchester, UK, 1995.

Patents

  1. A.M.Romankevich, V.V.Groll, O.A.Petlin, L.Ph.Karachun, R.I.Lupanova, "A generator of test vectors", Patent of the USSR, No. 1405058, 22.02.88., Int. Cl. G 06 F 11/26.

Statement on Research

Previous research

CTS research project

My Candidate of Technical Sciences (CTS) project was devoted to design for testability methods of synchronous VLSI circuits. The proposed approaches to designing testable VLSI circuits were based on random pattern test procedures because of their simplicity for alrorithmic and technical realizations.

PhD research project

Asynchronous design methodologies are a subject of growing research interest since they appear to offer benefits in low power applications and promise greater design modularity. However, before these advantages can be exploited commercially, it must be shown that asynchronous circuits can be tested effectively in volume production. My PhD thesis contains the results of research into various aspects of the design for testability of asynchronous circuits.

The focus of my PhD research project was on:

Experience in use and maintenance of VLSI CAD tools

CADENCE design environment

I have extensively used the VLSI design tools from Cadence design framework II including schematic entry, layout editor, place and route tools, design of tool interfaces in SKILL, circuit modelling using SPICE. I have been involved in the designing of some testable cells for the AMULET cell library.

ViewLogic CAD tools

I have used ViewLogic CAD tools in my demonstration work. This includes schematic and symbol entry, simulation and creating command files.

SIMIC design verification tools

I have used the SIMIC design verification tools in my research: circuit modelling, design of tester interface, stimulus verification with fault analysis.

VHDL

Also I have an experience of working with VHDL hardware description language including the design of a simple RISC microprocessor, implementation of various designs from behavioral models through to gate level implementations.

CAD tools for asynchronous circuits

I am familiar with such CAD tools as ASSASSIN and FORCAGE which I have used to design asynchronous control circuits described at the STG level.

I have an experience with the TANGRAM language for designing handshake circuits. A great deal of research has been done in the field of designing and testing of handshake circuits.

Social Activities

Sept. 1993 - present: Tutor in a Hall of Residence (Grosvenor Place, Grosvenor Street, Manchester, M1 7HR).

Sept. 1994 - present: Teacher of Russian in Grosvenor Place.

Feb. 1994 - Sept. 1995: President of Eastern European Students' Society at the University of Manchester.

Nov. 11-26, 1994: A translator for a group of eight politicians and two senior administrators from the Ukrainian Parliament attended a two week seminar in Great Britain, entitled "Making Democracy Work".

Hobbies

Sports: body-building, tennis, basketball, jogging.

Others: classical music.

Referees

  1. Prof. Steve B. Furber 
    2. Department of Computer Science 
University of Manchester 
Manchester, M13 9PL, UK
email: sfurber@cs.man.ac.uk
tel. +44 (0161) 275-6166; fax +44 (0161) 275-6202
  2. Dr. Jim D. Garside 
    3. Department of Computer Science, University of
Manchester, Manchester, M13 9PL, UK

email: jdg@cs.man.ac.uk
tel. +44 (0161) 275-6143; fax +44 (0161) 275-6202
  3. Dr. Linda E. M. Brackenbury 
    4. Department of Computer Science
University of Manchester
Manchester, M13 9PL, UK

email: lemb@cs.man.ac.uk
tel. +44 (0161) 275-6118; fax +44 (0161) 275-6202

Addresses for correspondence

Work address:

Room 2.25A
Department of Computer Science
Faculty of Science
University of Manchester
Oxford Road
Manchester, M13 9PL, UK

tel. +44 (0161) 275-6844

fax +44 (0161) 275-6202
    +44 (0161) 275-6236

email:   oleg@cs.man.ac.uk

Home address:

Room HC2
Grosvenor Place
Grosvenor Street
Manchester, M1 7HR, UK

tel. +44 (0161) 200-3190