From nowick@cs.columbia.edu Wed Nov 30 01:22:28 1994
Date: Tue, 29 Nov 94 20:13:14 EST
From: Steven Nowick
To: asynchronous-private@cs.columbia.edu
Subject: Re: Question concerning delay hazards
Content-Length: 1485
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Status: RO
From: "Peter A. Beerel"
Date: Wed, 23 Nov 1994 14:10:39 -0800 (PST)
Hello all,
I just thought I would add my two cents to the pile.
> My question was intended to find out if there exist methods assuming
> Input-Output mode which use conventional two-level logic / multi-level logic and
> which can take into account delay hazards.
In the speed-independent circuit domain, conventional two-level logic/multi-level
logic routines (ala espresso) can often generate circuits with delay hazards.
However, constrained two-level logic routines that feed C-elements and
yield correct speed-independent circuits has been studied by myself (Beerel
et. al, ICCAD '92) and others in the field (e.g., Kishinevsky et. al,
TAU '93, Lin et. al, DAC 91, and others). I have also started exploring
the use of multi-level logic in speed-independent circuits (Beerel et. al,
ICCAD '92 and TAU '93). In both cases, we are developing new minimization
techniques that take into account delay as well as other hazards. The
biggest challenge we see is to efficiently find gate decompositions that
preserve hazard-freedom (see Siegel et. al, ICCAD '94). We will have a
comprehensive technical report on our synthesis methodology available by
Dec 1.
Cheers,
Peter
-------------------
Peter A. Beerel pabeerel@eiger.usc.edu
EEB 350, MC 2562, Dept. of EE-Systems Office: 213-740-4481
University of Southern California FAX: 213-740-9803
Los Angeles, CA 90089-2562