From nowick@cs.columbia.edu Fri Mar 10 22:48:38 1995 Date: Fri, 10 Mar 95 17:34:55 EST From: Steven Nowick To: asynchronous-private@cs.columbia.edu Subject: [Rob Payne : Which FPGA product to use in async design?] Content-Length: 3121 X-Lines: 76 Status: RO From: Rob Payne Date: Fri, 10 Mar 1995 10:12:02 GMT [CORRECTION: the original questions on FPGA's are from John Cheng at Columbia University, not from me. -Steve Nowick] Steven Nowick writes: nowick> Question 1. Which of them are (seem to be) suitful for nowick> asynchronous circuits? In my view, the most critical factor in choosing your FPGA will be whether you can get directly at the architecture. Most suppliers hide you from the actual architecture through a set of technology mapping and routing/placement tools designed for synchronous designs. The hazard-free nature of your design and iso-chronic forks probably won't be preserved by these tools, so you really need to be able to get directly at the architecture. Some suppliers, such as the Xilinx LCA, don't give you the configuration format in their data-books (presumably so that you have to use their mapping tools), though you maybe able to get hold of the information from them. You're also going to need information on the routing delays to preserve iso-chronic forks. Secondly, since your going to have to do your own mapping to the FPGA, the simpler the architecture is to describe, the better. One of the fine-grain FPGAs such as the CLi6000 or Algotronix CAL would seem to fit the bill. Algotronix have now been taken over by Xilinx. The second generation CAL is due to be released this year. They seem to be interested in giving pre-releases of the specifications to various research groups to promote it in the academic world so they might be worth getting in touch with. Finally, if you're going for in-system reconfigurablity, then an architecture , again such as the CLi or CAL that map the configuration memory as SRAM rather than use a serial programming interface such as the Xilinx would be better. You can also read values back directly from the array with the CAL architecture (can't remember about the Cli) without having to interface with the edge of the array. nowick> Question 2. Do you know any other products may be suitful for nowick> asynchronous circuits? No. nowick> Question 3. Any experience or suggestion in implementing nowick> asynchronous circuits with FPGAs are welcomed. Most of the work on using current commercial FPGAs has concentrated on micro-pipeline style circuits. There's a fairly comprehenvsive list on my web page (url below). I'm actually developing a bundled-data style of architecture for my PhD. The other main work on a dedicated asynchronous architecture is the MONTAGE architecture (an asynchronous version of the Triptych architecture). My architecture is still under development and the MONTAGE architecture has yet to be mapped to silicon as far as I know. So I think you're stuck with using current synchronously-oriented FPGAs. nowick> Question 4. Any Email-address, WWW, or tel. no. related to the nowick> above products Time for some self-promotion. My own page has links to what I've found to be useful information. Try: http://www.dcs.ed.ac.uk/students/pg/rep/selfTimedFPGA/selfTimedFPGA.html Suggestions for imnprovements are welcome. Rob Payne.