From myers@enjoy.stanford.edu Tue Mar 7 22:04:27 1995 Date: Tue, 7 Mar 95 13:30:04 -0800 From: myers@enjoy.stanford.edu (Chris John Myers) To: asynchronous-private@hohum.Stanford.EDU Subject: electronic reports available Content-Length: 3021 X-Lines: 78 Status: RO I'd like to announce the availability of electronic versions of several theses, papers, and technical reports describing research done on asynchronous design at Stanford University. A list of the available publications is given below. They can be obtained by anonymous ftp from: havefun.stanford.edu. They reside pub/asynch/papers listed by the name given in parentheses under its corresponding cite below. Chris Myers myers@enjoy.stanford.edu Theses ------ P. A. Beerel, "CAD Tools for the Synthesis, Verification, and Testability of Robust Asynchronous Circuits", PhD thesis, Stanford University, 1994. (PAB-Thesis.ps.Z) K. Y. Yun, "Synthesis of Asynchronous Controllers for Heterogeneous Systems", PhD thesis, Stanford University, 1994. (KYY-Thesis.ps.Z) P. S. K. Siegel, "Automatic Technology Mapping for Asynchronous Designs", PhD thesis, Stanford University, 1995. (PSKS-Thesis.ps.Z) Journal Articles ---------------- C. J. Myers and T. H.-Y. Meng, "Synthesis of timed asynchronous circuits," in IEEE Transactions on VLSI Systems, 1(2), June, 1993. (TVLSI6_93.ps.Z and TVLSI_93fig.ps.Z) P. A. Beerel, C. J. Myers, and T. H.-Y. Meng, "Automatic synthesis of gate-level speed-independent circuits," submitted to IEEE Transactions on CAD, November, 1994 (also available as a Stanford University technical report CSL-TR-94-648). (CSL-TR-94-648.ps.Z) C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, "Automatic synthesis and verification of gate-level timed circuits," submitted to IEEE Transactions on CAD, January, 1995 (also available as a Stanford University technical report CSL-TR-94-652). (CSL-TR-94-652.ps.Z) Conference Papers ----------------- C. J. Myers and T. H.-Y. Meng, "Synthesis of timed asynchronous circuits," in IEEE International Conference on Computer Design, ICCD-1992, October, 1992. (ICCD92.ps.Z) T. G. Rokicki and C. J. Myers, "Automatic verification of timed circuits," in Computer Aided Verification, CAV '94, June, 1994. (CAV94.ps.Z) C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, "Automatic synthesis of gate-level timed circuits with choice," to appear at 1995 Chapel Hill Conference on Advanced Research in VLSI. (ARVLSI95.ps.Z) C. J. Myers, P. A. Beerel, and T. H.-Y. Meng, "Technology mapping of timed circuits," submitted to 2nd Working Conference on Asynchronous Design Methodologies. (LONDON95.ps.Z) Technical Reports ----------------- C. J. Myers and A. J. Martin, "The design of an asynchronous memory management unit", Tech. Rep. Caltech-CS-TR-93-30, California Institute of Technology, 1994. (CS-TR-93-30.ps.Z) C. J. Myers and T. H.-Y. Meng, "A uniform approach to the synthesis of synchronous and asynchronous circuits", Tech. Rep. CSL-TR-94-650, Stanford University, 1994. (CSL-TR-94-650.ps.Z and CSL-TR-94-650fig.ps.Z) C. J. Myers and T. H.-Y. Meng, "Automatic hazard-free decomposition of high-fanin gates in asynchronous circuit synthesis", Tech. Rep. CSL-TR-94-651, Stanford University, 1994. (CSL-TR-94-651.ps.Z and CSL-TR-94-651fig.ps.Z)