From Alex.Yakovlev@newcastle.ac.uk Sat Apr 30 18:37:31 1994
From: "Alex Yakovlev"
Date: Sat, 30 Apr 1994 18:24:30 +0100
>If you know of a good implementation of a sequencer device (a la Jo
>Ebergen), I will appreciate receiving information on that.
> The sequencer, to remind you, has two 2-phase request inputs
> and two 2-phase grant outputs, and a single 2-phase "next"
> control input. The devices arbitrates two simultaneous
> requests, etc.
Here is a ps file with one possible implementation of the 2-way
sequencer. It also contains its Signal Transition Graph spec.
At least, this is how I understood the behavioural description
of this device from Jo Ebergen's thesis (and your query above).
It seems to work fine (manual check). There can of course be
better solutions (in terms of performance and area) using logic
synthesis tools. But these would not be truly delay-insensitive
because they would rely on logic gates and not on the "standard"
DI components. I also expect some implementation on the so-called
generalised Decision-Wait (the one with an internal ME) because
it seems that 2-SEQ is exactly what the generalised DW is (if
I remember correctly). You would probably expect a better answer
about such a DW from some of the guys who work with DI components