3D v3.02, Mixed Asynchronous / Synchronous Synthesis Tool
SPECIFICATION:
Extended-burst-mode Specification (cf: ICCAD'93 "Unifying
Synchronous/Asynchronous State Machine Synthesis" by Yun and Dill)
Range of specifiable behavior:
1. Restricted multiple-input change (input burst) with don't-care
inputs allowed
2. Input choices based on sampling possibly glitchy signals
IMPLEMENTATION:
Target implementation is a combinational circuit with both primary
outputs and state variables fed back.
1. Two-level PLA description of outputs and state variables
2. Verilog netlist using a customizable CMOS standard cell/gate array
technology mapper
Note:
1. The 3D tools makes use of Steve Nowick's exact logic minimizer
(nowick@cs.columbia.edu) to generate minimized logic equations. An
alternative combinational logic minimizer based on BDD
descriptions are under investigation (ICCAD'94).
2. An algebraic technology mapper (included in the distribution)
generates a Verilog netlist from each two-level logic equation.
The CMOS library that comes with the mapper is easily
customizable.
DELAY MODEL:
Bounded wire delay model
CONNECTION WITH OTHER TOOLS:
The 3D tool has been incorporated as a part of a larger asynchronous
synthesis system called STETSON available from HP Labs.
AVAILABILITY:
3D v3.02 can be obtained through anonymous FTP from
snooze.stanford.edu. Associated
papers (ICCAD'93, EDAC'93, ICCAD'92, ICCD'92) are also available at the
same site.
Contact person:
Kenneth Y. Yun
kyy@paperchase.stanford.edu
CIS-015
Stanford University
Stanford, CA 94305
(415) 725-3646