Power efficiency is becoming a major concern in all areas of VLSI design and processing. The challenge for more power efficient chips and systems is presented at every level of design and production. Power consideration has already been seen at the following aspects: software, architecture, systems, CAD, logic, circuit, device, processing and material.
The special issue will focus on the design and processing technology of VLSI for Low-Power chips. It is our intention to promote cross fertilization among VLSI design and processing technology. All papers are encouraged to discuss the impact and the relationship their technologies/ideas/methods with the other aspects of chip production. For example, a new Low-Power circuit structure may want to discuss the superiorities or difficulties of the specific techniques in the reliability, testing and feasibility of mass production.
Topics in the following areas are solicited:
Tutorial papers which span multiple discipline are especially welcome. Deadline for submission is March 30, 1995. Notification of acceptance will be mailed by June, 1995. The accepted paper will appear in the Jan 1996 issue.
Questions regarding the special issue should be forwarded to the Guest Editors. Please submit 3 copies of an original, previously unpublished paper to:
Special Issue Guest Editor IJHSE
Prof. Farid Najm
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
209 Computer and Systems Research Laboratory
1308 W. Main Street
Urbana IL 61801