Asynchronous Superscalar Processors

J. Garside

Suitable for: ACS, CS(?)

Processor clock rates get faster all the time, and this is an "easy" way of increasing the performance of a computer. However this is no longer enough in the competitive world of microprocessor design, and other ways of speeding up processors are sought. One of the current favourite methods is a superscalar approach, where several instructions from a (supposedly) serial stream are issued simultaneously.

Most high performance processors are now issuing more than one instruction at once. Thus two, four, or even more instructions can be executed in each clock cycle. Unfortunately there are problems! A particular difficulty is caused by inter-instruction dependencies. For example if one instruction uses a result produced by the instruction preceding it in the source code they cannot be executed together because an operand will be missing. Dependencies reduce the number of instructions issued from the theoretical maximum - a processor which can issue four instructions at once may only execute about two on average.

Almost all the work on superscalar (or indeed any) microprocessors has studied synchronous (i.e. globally clocked) systems. The AMULET group is interested in asynchronous systems. These introduce some added problems, but may also allow different and novel solutions.

This project is intended to investigate the problem of superscalar issue in an asynchronous environment. This may be done by adapting existing synchronous techniques, developing novel architectures or exploiting characteristics of asynchronous systems such as the ability to vary the cycle time so that serial issue can be used, but performed many times faster than a typical "cycle". It is anticipated that results will be developed as software models, possibly using a language such as LARD or other purpose designed languages.