Performance analysis of an asynchronous bipolar datapath (ACS,CC)
L. E. M. Brackenbury

A 32-bit asynchronous datapath based on the ARM architecture has been designed and implemented in a high performance differential bipolar logic. The design, called TAMULET, comprises a full custom designed datapath and a standard cell control. It was expected, on the basis of gate speed, to run at least twice as fast as AMULET1. However, the actual performance did not match this expectation. Measurements on the chip indicate that the performance loss is in the control section rather than the datapath. The purpose of this project is to identify the features contributing to the overall speed of the system and to suggest how the potential performance might be realised if the control were redesigned.

Reference: R. Kelly, M.Sc. Thesis, University of Manchester, 1995.