Architectural modelling of a small synchronous RISC computer (ACS,CC)
L. E. M. Brackenbury

The STUMP processor is a small, simple, synchronous 16-bit RISC computer whose instruction set specification is used as the basis of laboratory exercises for the undergraduate, second year, engineering courses. The course on VLSI Systems Design uses a top-down hierarchical approach to take the design from its high level specification down to a gate and register level (called RTL).

Models have been written to check the behaviour of the system at the top, architectural and RTL levels. Unfortunately, all the models are simulated from the binary bits of the instruction fetched. While this is suitable for simulation at the RTL level, it is too low level for the higher levels as the explicit linking to particular bits inhibits system alternatives from being explored. The purpose of this project is therefore to investigate and choose how instructions can be specified at a higher level. This will then be used with a modified architectural model to examine the relative efficiency of architectural alternatives.

Reference: CS2242 Laboratory Manual, 1997