Design styles for high performance bipolar logic (ACS, CC)
L. E. M. Brackenbury

An asynchronous, clock-free approach is used in the CMOS designs of the AMULET research group because it has the potential for better performance, area and power than its synchronous counterpart. This arises because of the large area and power consumed by the clock driver circuits and the need to design for worst case conditions in these designs. Furthermore, in a synchronous system, all units operate from the clock and result in transitions which dissipate power regardless of whether the unit does useful work. This does not arise in asynchronous systems because they are data driven and so only make transitions when they operate.

Most high performance bipolar circuits are constant current. Therefore the power is constant regardless of the number of transitions and the case for adopting an asynchronous approach is not as clear as for CMOS technology. The aim of this project therefore is to compare power, performance and area for an asynchronous and synchronous approach on a substantial section of high performance, constant current, bipolar logic in order to determine the relative merits of these design styles.

Reference: R. Kelly, M.Sc. Thesis, University of Manchester, 1995.