An Analysis of Asynchronous Processor Pipelines (ACS)
The AMULET group has developed two asynchronous implementations of the ARM microprocessor, each using a slightly different pipeline structure and both different from the 3-stage pipeline used on the clocked ARM. Recently, ARM Limited has announced the ARM8 and Digital the StrongARM, each of which uses a different 5-stage pipeline.
The goal of this project is to investigate the relative merits of each of these pipelines and to evaluate the benefits of adapting a 5-stage pipeline to asynchronous implementation for a future AMULET design.
The work will involve high-level modelling in VHDL, C or one of the new asynchronous hardware modelling tools developed recently in the Department to give quantitative performance estimates for the various pipeline structures.