Timing Verification for Asynchronous Design
R.M.Davies and J.V.Woods
This paper describes a technique for verifying timing conditions inherent
in self-timed VLSI designs that make use of the micropipeline design
strategy. By checking bundling constraints during simulations, design
faults may be detected, whilst timing information extracted during the
processing may be used to identify modules requiring optimisation. These
analyses may be built around existing simulators.
paper (28K compressed).