The Design of an Asynchronous VHDL Synthesizer
S-Y. Tan, S. B. Furber and W-F. Yen
Abstract
This paper presents a straightforward approach for synthesizing a standard VHDL
description of an asynchronous circuit from a behavioural VHDL description. The
asynchronous circuit style is based on `micropipelines', a style currently used
to develop asynchronous microprocessors at Manchester University. The rules of
partition and conversion which are used to implement the synthesizer are also
described. The synthesizer greatly reduces the design time of a complex
micropipeline circuit.
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