Register Locking in an Asynchronous Microprocessor
N.C. Paver, P. Day, S.B. Furber, J.D. Garside, J.V. Woods
A high performance register bank is a central component of a RISC
processor. A novel register bank design has been developed, as an integral
part of a self-timed implementation of a commercial RISC microprocessor,
to address the problem of register interlocking in an asynchronous
micropipelined execution unit.
The challenge in an asynchronous design is to maintain coherent register
operation while allowing concurrent read and write accesses with arbitrary
timing. The solution presented here includes a novel arbiter-free locking
mechanism which enables efficient read operations in the presence of
multiple pending write operations.