## Random Testing of Asynchronous VLSI Circuits

O. Petlin

### Abstract

Asynchronous VLSI designs are becoming an intensive area of research
due to their advantages in comparison with synchronous circuits, such
as the absence of the clock distribution problem, lower power
consumption and higher performance. The work described in this thesis
is an attempt to find possible ways to test asynchronous VLSI circuits
using random (or, more accurately, pseudo-random) patterns. The main
results have been obtained in the field of random testing of stuck-at
faults in micropipelines.
An asynchronous random testing interface has been designed which
includes an asynchronous pseudo-random pattern generator and an
asynchronous parallel signature analyser. A program model of the
universal pseudo-random pattern generator has been developed. The
universal pseudo-random pattern generator can produce multi-bit
pseudo-random sequences without an obvious shift operation and it can
also produce weighted pseudo-random test patterns.

Mathematical expressions have been derived for predicting the test
length for random pattern testing of logic blocks of micropipelines by
applying equiprobable and weighted random patterns to the inputs.

The probabilistic properties of the n-input Muller-C element have been
investigated. It is shown that the optimal random test procedure for
the n-input Muller-C element is random testing using equiprobable input
signals. Using the probabilistic properties of the Muller-C element and
multiplexers incorporated into the circuit a certain class of
asynchronous networks can be designed for random pattern testability.
It is also shown how it is possible to produce pseudo-random patterns
to detect all stuck-at faults in micropipelines.

Full text available by ftp.