A high proportion of the energy consumption of a microprocessor system is consumed within the caches and external RAM. A significant proportion of memory traffic relates to allocating and de-allocating registers. Register file architectures are proposed to reduce this traffic. Of the schemes investigated, memory mapped registers held in a small separate register cache, has proved to perform well and be energy efficient.
A new branch architecture, which has the potential to eliminate or significantly reduce the miss-prediction penalty of branches through prefetching, will be examined. This scheme, which also improves the hit-rate, employs a pair of instructions. It allows the potential branch target to be prefetched into the cache and into the first stages of a shadow pipeline, before the outcome of the condition evaluation is known and thus reduce or eliminate branch penalties. The overall effect is improved performance. However due to increased cache traffic, the scheme is not energy efficient.
In conclusion, the energy efficiency of a RISC microprocessor can be improved by reducing the average instruction size. The memory traffic can be reduced and the energy efficiency consequently improved, if the allocation/de-allocation of registers can be organised such that interaction with the data cache is minimised. The examined branch architecture may improve performance but is not energy efficient. However, it shows that the Achilles' heel for performance is also the Achilles' heel for energy efficiency.