About me
I am currently employed on OMI-EXACT ( EXploitation of Asynchronous
Circuit Techniques - ESPRIT project 6143) project as a Research
Associate. During the EXACT project I have completed an MSc entitled
Low Power Implementations of an I2C IO Expander and I have started a
Phd based on low power asynchronous digital design.
My responsibilities have involved the development of a Low Power CMOS
cell library which is available for ftp on request
cf@cs.man.ac.uk and the
development of a new design flow incorporating Tangram Silicon Compiler developed at
Philips Research Labs, Eindhoven. The new design flow has been named the
hybrid design environment
since it allows the system designer to apply
optimisations in schematics or layout and to interface to full custom
designs in the same cad framework. To achieve this an interface to Cadence design framework has been
implemented which translates the intermediate handshake circuit
description into a hierachial, bounded-delay, circuit description in
Verilog and streams it into Cadence DFII as a schematic.
To complete the environment simulation tools have been developed in collaboration with Genashor, NJ and interfaced to the Cadence Open Simulation Environment.
Publications
Aaron Ashkinazy, Doug Edwards, Craig Farnsworth, Gary Gendel and Shiv Sikand
Tools for Validating Asynchronous Digital
Circuits
Proceedings of International Symposium on Advanced Research in Asynchronous
Circuits and Systems, IEEE Computer Society Technical Committee on VLSI
Salt Lake City, Utah, USA Nov. 3-5th 1994
Craig Farnsworth, Doug Edwards, Shiv Sikand
Utilising Dynamic Logic for Low Power
Consumption in Asynchronous Circuits
Proceedings of International Symposium on Advanced Research in Asynchronous
Circuits and Systems, IEEE Computer Society Technical Committee on VLSI
Salt Lake City, Utah, USA Nov. 3-5th 1994
Shannon V. Morton, Craig Farnsworth, San Appleton, Michael J. Liebelt.
Asynchronous Pipelining Techniques and Applications
Submitted to Microelectronics95, Adelaide, Australia. 17 July 1995.
Craig Farnsworth, Doug Edwards, Jianwei Liu and Shiv Sikand
A Hybrid Asynchronous System Design Environment.
Submitted to the 2nd Working Conference on Asynchronous Design Methodologies
South Bank University, London. 30-31 May 1995
Low Power Cell Library
The Beta Release of our Low Power Cell Library designed on ES2s 1
micron CMOS process is available. Access to this process is available
via Eurochip. This includes all standard boolean functions, inverters
and buffers, MullerC-element family, Muxes, Storage elements and
2-phase micropipeline components. Datasheets are also available.
The methodology used to design the low power cell library is described in EXACT project deliverable C4: DelivC4
Mail cf@cs.man.ac.uk for details