An asynchronous random testing interface has been designed which includes an asynchronous pseudo-random pattern generator and an asynchronous parallel signature analyser. A program model of the universal pseudo-random pattern generator has been developed. The universal pseudo-random pattern generator can produce multi-bit pseudo-random sequences without an obvious shift operation and it can also produce weighted pseudo-random test patterns.
Mathematical expressions have been derived for predicting the test length for random pattern testing of logic blocks of micropipelines by applying equiprobable and weighted random patterns to the inputs.
The probabilistic properties of the n-input Muller-C element have been investigated. It is shown that the optimal random test procedure for the n-input Muller-C element is random testing using equiprobable input signals. Using the probabilistic properties of the Muller-C element and multiplexers incorporated into the circuit a certain class of asynchronous networks can be designed for random pattern testability. It is also shown how it is possible to produce pseudo-random patterns to detect all stuck-at faults in micropipelines.
O.A.Petlin, "Random testing of asynchronous VLSI circuits", M.Sc. Thesis, Department of Computer Science, University of Manchester, October, 1994.
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Asynchronous design methodologies are a subject of growing research interest since they appear to offer benefits in low power applications and promise greater design modularity. However, before these advantages can be exploited commercially, it must be shown that asynchronous circuits can be tested effectively in volume production. This thesis presents the results of research into various aspects of the design for testability of asynchronous circuits.
Low power is often achieved by minimising circuit activity. However, testable designs require high transition probabilities. It is shown that design for testability and design for low power are in direct conflict. As a result, the more testable a circuit is, the more power it consumes. The resolution of this conflict can be found in the separation of normal operation and test modes. In test mode the circuit activity is increased, dissipating more power.
Many asynchronous designs use Muller C-elements in a large variety of applications including both control and data paths. Testable CMOS designs for C-elements are presented which provide for the detection of transistor stuck-at and stuck-open faults.
The scan test technique is used to test stuck-at and delay faults in micropipelines. This technique is generalised to the design for testability of either two-phase or four-phase micropipelines. An asynchronous built-in self test (BIST) micropipeline design based on the BILBO technique is presented. The proposed design for the BILBO register allows stuck-at and delay faults to be detected inside the combinational circuits of the micropipeline.
Structural designs for random pattern testability techniques applicable to asynchronous sequential circuits are described. The proposed random test procedure provides for the detection of all single stuck-at faults in the control and data paths of the sequential circuit under test, reducing the overall test complexity to the testing of its combinational network.
Case studies of testable implementations of some high-level asynchronous functions, including an adder and a block sorter, are analysed for their testability, performance and area cost. These designs show that, as expected, there is a trade-off to be made between testability and cost. However, satisfactory testability can be achieved for a circuit designed with a small area overhead for test circuitry and little performance degradation.
O.A.Petlin, "Design for testability of asynchronous VLSI circuits", Ph.D. Thesis, Department of Computer Science, University of Manchester, submitted in January, 1996.
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