Minimisation of Branch disruption.(ACS/CC)

Branch instructions have the potential to disrupt instruction flow and in practice a change of control flow every five or six instructions is not uncommon. These changes in control flow make it difficult to maintain a flow of instructions into an execution pipeline and hence place a limit on achievable performance.

Various strategies have been employed to address this problem including assumptions that conditional branches will always be taken, that a branch will behave as it did when last encountered and on the basis of "hints" provided by a compiler.

A high proportion of branches are used for "loop-closing", here any conventional strategy will fail to predict the branch outcome once. This may be of little consequence where the number of loop iterations is large but may be significant when small. One approach to this problem is to incorporate a specific "Start-Loop" instruction which would load an iteration counter and set the length of the loop; the loop control hardware would then determine whether or not a branch back should be taken with the possibility of 100% prediction accuracy.

The aim of the project would be to analyze program traces to establish the value of introducing such schemes into a processor. Tracing programs provide dynamic instruction execution information on any chosen benchmark. This data can be analyzed to identify branch instructions, their target addresses and whether or not they were taken. From this information the performance value of introducing special instructions such as "Start-Loop" should be evaluated with the aim of influencing future processor architectures.

REQUISITES: C programming and Compiler familiarity.