Multi-level Caching (ACS/CC)

The performance of a modern RISC processor is constrained by efficiency of register usage and the performance of its memory sub-system with regard to loading/write-back of register contents and the access of instruction data. The memory system "front-line" is the cache and high performance here is vital.

Cache "performance" usually embraces "hit-rate" and "cycle time"; the former determines the frequency of main-memory references and hence of pipeline stalls; the latter determines the execution time of instructions obtaining a cache hit. For a given technology and organisation a small cache will usually yield a faster cycle-time than a large one but the cache size must be sufficient to yield an acceptably high hit-rate. To achieve required size-performance compromises unitary caches may be divided to cache instruction and operand data separately or multi-level strategies may be employed.

The aim of the project is to investigate the performance effectiveness of multi-level caching systems. This will involve the development of a multi-level cache simulation system; this will then be used to gather performance statistics when used in conjunction with a set of available program traces. Cache parameters will be varied to establish practical guidelines for cache parameters at each level.

Requisites: C programming competence + architectural interest.