Advanced Processor Technologies Home
APT Advanced Processor Technologies Research Group

Alex Rast

My photo

Research Associate
Room number: IT-302
Other contact details

I am a Research Associate (and Ph.D. student) in the School Of Computer Science at the University of Manchester, UK.

Research Interests

Neural Network Hardware Blocks. Currently neural network design, especially in hardware, tends to be a semi-empirical exercise. One of the outstanding problems is that while there are multiple architectures, each of them has its own associated theory - with little to relate them except at the highest levels of abstraction. I hope to remedy both the theoretical deficiency and more importantly, the practical one by developing blocks, a little like drop-in IP, that a designer can use more or less effortlessly in order to include neural networks in a design.

Neural Interconnect and Synchronisation. The spiking model of neural function has revealed the possible (probable?) presence of neuronal synchronisation - that is, a group of neurons firing with the same timing frequency. If phase-sensitive information coding happens in the brain (as now seems likely) there must be some mechanism of achieving that synchronisation - especially over long distances where delays are significant. Just as importantly, these long-range connections raise a host of questions regarding how they are set up. If in the brain neurons group into distinct "blocks" - as per the above - and these blocks then connect together, how do you set up the interconnect so as to provide meaningful communication between 2 parts whose purpose and structure might be quite different? My suspicion is that these questions of timing and configuration are interlinked, and am developing models to explain them.

Synthesis-oriented Design of Neural Network Hardware With Off-the-shelf Components. There have been many attempts to develop dedicated neural IC's in the past, most of them meeting with varying degrees of disinterest or disappointing results. Much of the problem seems to be that many if not most of these designs are highly specialised, full-custom designs developed to implement a specific neural architecture. This rather limits their usefulness. What we need in order to turn a neural chip into a successful component is something much more general-purpose, making fewer assumptions about the architectures to be implemented thereon. In addition, if we build these using off-the-shelf IP (Intellectual Property - basically standardised design elements) it will be familiar to many more users and minimises implementation headaches as well. I am involved in the design of a first-generation prototype of what such chips might look like.

Ignore this if you're not doing OpenOffice debugging: Sample file with page breaks that you can't edit