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Mahdi Jelodari Mamaghani


"Computer Science is not just about coding to get a job done,
it's also about broader thinking skills like computational thinking
and abstraction and modeling and design."
Simon Peyton Jones

My photo

Postgraduate Student
Room number: IT-302
My homepage - eTeak page
My Google Scholar
My Online CV - PDF
Other contact details © 2016 - Mahdi Jelodari

I am an EPSRC research fellow at the School Of Computer Science at the University of Manchester, UK. I am a member of the Advanced Processor Technologies group led by Professor Steve Furber. I completed my PhD degree under supervision of Dr James Garside and Dr Vasilis F. Pavlidis. I received my Bachelor's degree in Computer Engineering in 2012 from the University of Tehran under supervision of Prof. Nasser Yazdani. I've also joined the IEEE community in 2010.

What am I working on? Basically I am an Asynchronologist. My research focused on developing EDA Flows and techniques capable of synthesising GALS (Globally Asynchronous Locally Synchronous) systems from Higher-levels of abstraction. In this respect, I leverage asynchronous/elastic techniques to seperate timing from functionality at design stage which simplifies the development process of the heterogeneous SoCs and favours designer's productivity. eTeak is a HLS framework designed during the course of my PhD for this purpose supported under GAELS project (Funded by EPSRC under research grant EP/I038306/1). My latest achievement (De-Elastisation) in this area is recognised as a promising approach toward high-level GALS synthesis by the EDA community in europe. You can also check me out on Uiversity of Manchester's seasonal newsletter: CS Newsletter - Spring 2015

Currently I'm involved in directing the FPGA acceleration framework at Reconfigure.io.

My PhD research contributions can be listed as follows:
  • "eTeak": A synchronous elastic dataflow syntehsis framework.
  • "RTL re-synthesis": Automatic transformation of dataflows to synchronous sequential machines (FSMs).
  • "De-Elastisation": Selectively transforming asynchronous dataflow models to synchronous circuits.
  • "Automatic Clock (AutoCLK)": The process of introducing a common timing discipline to an asynchronous synthesis flow.


  • eTeak group of the University of Manchester supprts Free and Open Source Silicon Fundation (FOSSI).
    Collaborate to eTeak by forking the project on Github: eTeak
    Currently eTeak is under development. For further information please don't hesitate to contact me.

    Research Interests

  • Energy Efficient Computing and Synthesis
  • High-Level Synthesis Flows and CAD Development
  • Integrated Synchronous-Asynchronous Design Schemes
  • Globally Asynchronous Locally Synchronous (GALS-SoC) Design
  • High-Performance Data Streaming Processors
  • FPGA-accelerated Hardware Simulators
  • My interest

    Awards & Honours

  • Received the EPSRC Doctoral Prize Fellowship 2015/17 - The University of Manchester
  • Selected for the final round of UK ICT Pioneers 2015
  • DATE Best IP Award 2015 sponsored by Cadence
  • DASS scholarship joint with DAC 2013 and MICRO 2014 Travel Grant
  • EPSRC Full Research Scholar Award for 3 years under grant EP/I038306/1, 2012
  • Among the top 5% of the computer engineering students at the ECE Department of the University of Tehran
  • Innovative Idea Award by the Science and Innovation Park of the University of Tehran for the proposal titled "Intelligent Navigation System", 2011 / patented under (Iran Patent No. 390070566).
  • Ranked 634th among 350,000 participants in the nationwide university exam, 2007
  • Semi-finalist in the Iran National Mathematics Olympiad, 2004
  • Peer-reviewed Publications

    14. Mahdi Jelodari Mamaghani, Rob Taylor, "The Synthesis Path for Transforming "Go" Programs into Hardware Deployable on FPGA-based Cloud Infrastructures," US Patent, App No 62/412,376

    13. Ana Lava, Mahdi Jelodari Mamaghani, Siamak Mohammadi, Steve Furber, "Application-aware Retiming of Accelerators: A Data-Driven Approach," (submitted to) IEEE Design and Test Journal - special issue on accelerator design in Data Centers, October 2016.

    12. Mahdi Jelodari Mamaghani, Milos Krtic, Jim Garside, "Automatic Clock (AutoCLK): A Promising Approach Towards GALSification," In Proc. of 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2016 PDF (197K) Slides

    11. Mahdi Jelodari Mamaghani, Danil Sokolov, Jim Garside, "Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis," In Proc. of the 16th International Conference on Application of Concurrency to System Design (ACSD), Poland, June 2016 PDF (524K)

    10. Mahdi Jelodari Mamaghani, Jim Garside, Doug Edwards, "De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits," (to appear) IEEE/ACM conference on Design Automation and Test in Europe (DATE), March 2015, Gernoble, France. [DATE Best IP Award Winner] PDF (757K)

    9. Mahdi Jelodari Mamaghani, Jim Garside, Will Toms, Doug Edwards, "Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA," The Euromicro Conference on Digital System Design (DSD), August 2014, Verona, Italy. PDF (524K)

    8. Mahdi Jelodari Mamaghani, Will Toms, Andrew Bardsley, Jim Garside, "Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain," Intl. Symposium on Asynchronous Circuits and Systems (ASYNC), May 2014, Potsdam, Germany.

    7. Mahdi Jelodari Mamaghani, Jim Garside, "High-level Synthesis of GALS Systems," Workshop on Designing with Uncertainty - Opportunities and Challenges (PAnDA), March 2014, York ,UK.

    6. Mahdi Jelodari Mamaghani, Will Toms, Jim Garside, "eTeak: A Data-Driven Synchronous Elastic Synthesiser," Intl. Conference on Application of Concurrency to System Design (ACSD), July 2013, Barcelona, Spain.

    5. Stephen A. Edwards, "MEMOCODE 2012 hardware/software cdesign contest: DNA sequence aligner," In Proc of 10th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE), Virginia, US. July 2012.

    4. Mahdi Jelodari Mamaghani, Mahan Molkara, Alireza Hoseini, Behnam khodabandeloo, Siamak Mohammadi, "A Centralized RSSI-Based Localization Algorithm for Wireless sensor networks," In Proc. of 4th Natl Conference of Command, Control, Communications, Computers and Intelligence (IC4I), Tehran, Iran. November 2011.

    3. Alireza Hoseini, Behnam khodabandeloo, Mahdi Jelodari Mamaghani, Siamak Mohammadi, "Hardware and Software Implementation of a Wireless Sensor Node (WSN) with High Flexibility," In Proc. of 4th National Confeence of Command, Control, Communications, Computers and Intelligence (IC4I), Tehran, Iran. November 2011.

    2. Alireza Hoseini, Mahdi Jelodari Mamaghani, Behnam khodabandeloo, Mahan Molkara, Nasser Yazdani, "WNA: Wireless Network Analyzer for High Throughput Wireless LANs," In Proc. of 5th Int'l Symp of Telecommunication (IST), Iran Telecommunication Research Center, Tehran, Iran. December 2010.

    1. Alireza Hoseini, Behnam khodabandeloo, Mahdi Jelodari Mamaghani, Peyman Teymoori, Nasser Yazdani, "High Throughpu Low Power CCMP Architecture for Very High Speed Wireless LAN," In Proc. of 15th CSI Int'l Symp. of Computer Architecture and Digital Systems (CADS), IPM, Tehran, Iran. September 2010.

    News & Updates

  • Updated on 1st December 2016
  • [USC Visiting Scholar]Back to the UK from LA. Had a great time working with the VLSI/CAD lab of USC under Prof. Peter Beerel.

  • Updated on 10th September 2016
  • Will be an exchange researcher under Prof. Peter Beerel @ University of Southern California for couple of months. I will be working on Dynamic Architecture Scaling at CAD/VLSI group.

  • Updated on 15th-16th August 2016
  • Visiting Computer Laboratory in Cambridge University, UK.

  • Updated on 8th August 2016
  • Submitted our first U of Manchester- U of Tehran collab paper to Memocode 2016.

  • Updated on 21st July 2016
  • [PhD Degree Award]Officially graduated from the University of Manchetser.

  • Updated on 20th July 2016
  • Attended in Alex Yakovlev's Festschrift event in Newcastle. Was great to meet Prof Peter Chaung and asynchronous folk again.

  • Updated on 22nd June 2016
  • Attending ACSD'16 in Torun, Poland. Will be presenting my paper and possibly demonstrating eTeak which is open source now and is available to public.

  • Updated on 23rd May 2016
  • Industrial-Academic collaboration between the University of Manchester (APT) and Codethink LTD. (Nerabus) is established.

  • Updated on 22nd April 2016
  • Visited the Router research laboratory at Tehran University. Also explored the possiblities for collaboration toward HW infrastructure development with Prof. Nasser Yazdani.

    Updated on 17th April 2016
  • At EPSRC workshop on research sandpit our team won the best research proposal on "Maintaining and improving life style as a solution to the aging problem in UK"

  • Updated on 22nd - 24th March 2016
  • [IHP - Visiting Researcher]Visited IHP Microelectronis in Germany, and gave a talk on eTeak synthesis framework. I and Dr Milos Krstic also discussed the possiblities on automatic GALSification. Meanwhile our paper entitiled "Automatic Clock: A Promising Approach Toward GALSification" got accepted to ASYNC 2016.

  • Updated on 18th March 2016
  • [ACSD'2016]Our paper entitiled "Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis" got accepted to ACSD. This work was a collaboration with the University of Newcastle.

  • Updated on 14th - 18th March 2016
  • Attended at DATE 2016. Congradulation to my friend, Abbas Rahimi, for winnnig the Best PhD Thesis Award this year! I did a demo on eTeak at University Booth entitiled "ASYNCHRONOUS DATAFLOWS SYNTHESIS ONTO FPGAS USING THE eTEAK FRAMEWORK".

  • Updated on 1st Febreury 2016
  • [PhD-viva]Passed the viva (aka PhD defense exam) successfully with Aii. Thanks to Prof. Jordi Cortadella for his valuable feedback.

  • Updated on 4th December 2015
  • Submitted the thesis entitled: High-level Synthesis of Elasticity: From Models to Circuits.

  • Updated on 11th November 2015
  • As Rob Pike clearly presented in his talk "Concurrency is not parallelism" and I believe this has become obvious for hardware folks in the past decade, particularly for high-level synthesis community. In this regard I have developed a CSP-model of the prime generator which has been the favorite example of the go community in the past 20 years. I have synthesised the model into hardware and the results comparing the software implementation against hardware counterpart will be released soon!

  • Updated on 13th October 2015
  • [EPSRC Doctoral Prize Fellowship] Today I was awarded the EPSRC Doctoral Prize Fellowship! This research grant, starting from December 1st, is allocated to my proposal entitled "Energy-centric Synthesis of GALS Systems". This valuable chance by the University of Manchester allows me to pursue a career in research.

  • Updated on 1st October 2015
  • Media Training Course @ EPSRC Head Office in Swindon towards the UK ICT Pioneers 2015.

  • Updated on 14th Sept 2015
  • [UK ICT Pioneers 2015] Selected proposal for the final round of UK ICT Pioneers 2015 to be held in QE II Conference Center in London on October 29th.

  • Updated on 29th August 2015
  • Started collaborating with the DSD Lab under Dr Mohammadi, the University of Tehran.

  • Updated on 8th July 2015
  • eTeak page just updated and the latest version of eTeak is avaliable to download.

  • Updated on 17th June 2015
  • Back from Newcastle. Had a very productive meeting with Prof. Yakovlev on the "eTeak as a Framework" subject.

  • Updated on 5th June 2015
  • Selected for the 2nd round of the UK ICT Pioneers Competition.

  • Updated on 18th May 2015
  • The first seminar of "By PhD students for PhD students" got organised by Mentors team succsessfully.

  • Updated on 12th March 2015
  • [DATE'15 - eScholarID:261063] The paper titled "De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits" received the DATE Best IP Award 2015 sponsored by Cadence. PDF (757K)

  • Updated on 4th February 2015
  • Back from RAL (Rutherford Appleton Laboratory) took a course on Xilinx Vivado (High Level Synthesis) design suite. Also got a ZYBO board for free which has a Zync-7000 FPGA on it with an ARM cortex-9 dual-core processor and additional CLBs. I think it's big enough to let me look at Synchronous Elastic + De-Elastisised SoCs.

  • Updated on 1st January 2015
  • I would like to wish everyone a fant├ística 2015 and may all your new year's resolutions (particularly thesis write ups) come true :-)

  • Updated on 17th December 2014
  • [MICRO'14] I'm back from Cambridge, attended Micro'14. I also participated in the Hot Debate. The proposition was: It is the end of the road for the von Neumann architecture. I was quite amused with this debate. Among bebaters were Steve Furber supporting the modern architectures and Yale Patt from the opposite party supporting the von Neumann architectures (sequential systems). And my vote was a Yes! to the modern architecture.

  • Updated on 10th December 2014
  • Mission accomplished. The paper titled "Empirical Evaluation of Asynchronous Dataflow De-Elastisation vs. Synchronous High-level Synthesis", submitted to a conference... :)

  • Updated on 31st October 2014
  • Cool! the paper entitled "De-Elastisation: From Asynchronous Dataflows to Synchronous Cicruits" got accepted at DATE'15. It will be held in Grenoble, France on 9th-13th March next year! ;)

  • Updated on 29th October 2014
  • I presented my work today @ the University of Manchesters' Research Symposium. Apparently the school has not considered a 'Best Presenter Award' this year, which totally pissed me off! :) btw, The slides will be available here soon.

  • Updated on 19th September 2014
  • Task accomplished: A paper entitled "De-Elastisation: From Asynchronous Dataflows to Synchronous Cicruits" submitted to a conference.

  • Updated on 29th August 2014
  • The paper entitled "Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA" presented @ the 17th EuroMicro Conference on DSD'14. PDF (173K)

  • Updated on 24th July 2014
  • The De-Elasticised verion of the SSEM processor runs almost 3x faster than its asynchronous counterpart. For more information please wait for the next publication! :)

  • Updated on 4th July 2014
  • Passed the second year Viva successfully! :)

  • Updated on 19th June 2014
  • [DSD'14 - eScholarID:232298] The paper entitled "Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA" got accepted in the Euromicro Conference on Digital System Design 2014. PDF (1046K)

  • Updated on 28th May 2014
  • Back from the Async'14. Now on, you can follow the updates on eTeak from here: eTeak
    You can also check eTeak Demo @ ASYNC 2014. In this video a brief introduction to eTeak is given including 1) a protocol-level post-simulation visual environment based on the synchronous elastic protocol, and 2) Make FSM: which provides eTeak a mechanism to explore the design space by transforming handshake-based fine-grained structures to RTL-based FSMs through re-synthesis.

  • Updated on 20th April 2014
  • Task accomplished: Just submitted my work to the Euromicro Conference on Digital System Design 2014. For more information please wait for the next update :-)

  • Updated on 19th March 2014
  • [ASYNC'14 - eScholarID: 229597] The paper entitled "Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain" got accepted in the ASYNC'14 Tool/Demo Session. PDF (416K)

  • Updated on 5th March 2014
  • Granted a £200 bursary from the Designing with Uncertainty - Opportunities & Challenges workshop towards Travel and Accommodation costs.

  • Updated on 21st February 2014
  • [PAnDA'14 - eScholarID:229596] The abstract entitled "High-level Synthesis of GALS Systems" got accepted in the "Designing with Uncertainty - Opportunities & Challenges" workshop. PDF (115K)

  • Updated on 12th December 2013
  • Currently I am working on a De-Elastisiser/RTL Transformer. A systematic optimisation engine to remove the fine-grained elasticity away using synchronous EDAs. I hope eventually will end up with a synthesisable polychronous framework capable of synthesising the integration of synchrony and asynchrony. The coolest part is that the designer will be able to use a unified language to fulfil this integration.

  • Updated on 8th December 2013
  • Synchronous Elastic Sparkler runs @ 1.6GHz. Sparkler is a cut-off version of SPARC v8 architecture. The Balsa description of it is implemented by Andrew Bardsley in almost 1k lines of Balsa in 2007.

  • Updated on 6th November 2013
  • My first case study was the Manchester Small-Scale Experimental Machine (SSEM), world's first stored-program computer. The Balsa description for SSEM is developed by Andrew Bardsley and it has been synthesised and tested through the Balsa synthesis system. Now I have a synchronous elastic version of it which means you don't need to be concerned about communication and computation delays. It's latency insensitive! It runs @ 740MHz with an effective CPU speed of 41.6 MIPS. Yes 38K faster than the first verion which came out in 1948!

  • Updated on October 2013
  • Presented a poster in the School's Research Symposium which was sponsored by IBM. The poster propses the general idea of my research. PDF (316K)

  • Updated on August 2013
  • Submitted my first year report entitled "High-Level Synthesis of Elastic Logic". It will become available online after the review process.

  • Updated on June 2013
  • [ACSD'13 - eScholarID: 210181] eTeak emerged as a Synchronous Elastic Synthesis System to transform the Fine-grained Dataflow networks from the asynchronous domian to the synchronous domain.
    eTeak: A Data-driven Synchronous Elastic Synthesiser  PDF (130K)

  • Updated on July 2012
  • My Phd start off!