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APT Advanced Processor Technologies Research Group

Research in Transactional Memory

[Lee-TM Benchmark] [TM Publications] [Jamaica Project (predecessor)]

Transactional memory proposes an alternative synchronization primitive to traditional locks. Its promise is to simplify the software development of multi-threaded applications while at the same time delivering similar performance to parallel applications written using (complex and error prone) fine grain locking.

This website describes our research activities on Transactional Memory (TM). Our interest covers a broad range of TM topics, including applications (Lee-TM Benchmark [1, 4]), hardware TM [5, 9, 15, 17], software TM [3, 7, 16, 19, 20], and contention management [2, 6, 8, 10, 13, 14, 15].

Motivation

The present and future of processor architectures has been confirmed as multi-core (e.g. Intel's and AMD's dual core and quad core chips or Sun Microsystems's Niagara). Multicore processors set a new precedent for software developers: software will need to be multithreaded to take advantage of future generations of processors. Now more than ever, it is critical that we codevelop concurrent software abstractions and computer architectures.

TM in a Nutshell

TM is inspired by transactions from databases and, with TM, developers simply label as transactions those blocks of code that access shared data. This relieves the developer of the need to remember which lock protects which variable, and ensuring the use of a specific lock acquisition order to avoid deadlock. It is the responsibility of the TM system, either implemented in hardware or in software, to maintain atomicity, consistency and isolation for each transaction.

A key advantage of TM is its promise of being able to compose software, whereas locks or messages do not compose. Another interesting feature is optimistic concurrency: transactions can be executed speculatively and when found to conflict with other transactions can be aborted. This optimistic view of concurrency can exploit more parallelism than the pessimistic view supported by traditional locks and semaphores.

Software TM

We have developed Manchester University Transactions for Scala (MUTS) [19,20]. MUTS is a Software Transactional Memory System for Scala and Java. It builds on the existing work done with Deuce STM to provide transactional memory for Scala. The granularity of these transactions can range from single lines of code to transactions spanning many objects and methods across many different classes both currently compiled and already compiled.

Hardware TM

Our Hardware TM system is the first to treat objects as first class entities in hardware. The approach is similar to hardware support of paged virtual memory using a virtually addressed cache and a TLB, and is based on a cache hierarchy that allows addressing objects by their unique identifiers. The object-aware HTM elegantly allows cache overflows of uncommitted data and enables a novel commit and conflict detection mechanism.

Given that the large majority of new applications are developed using Object-Oriented (OO) languages, with more than 60% relying on managed runtime systems, we are investigating computer architectures that target specifically these applications without precluding the execution of C or other non-OO languages. A key benefit of our object-aware hardware TM is to reduce inter-core bandwidth demands.

Contention Management

A conflict between any two transactions invokes contention management to decide which transaction should be aborted. Our experience with TM applications (e.g. Lee-TM Benchmark) found that they may exhibit fluctuating amounts of contention during execution: executing large numbers of transactions concurrently during phases of high contention leads to poor resource usage, and executing too few transactions concurrently during phases with low contention leads to poor performance.

We introduced and evaluated adaptive concurrency control, the first attempt to dynamically adjust the number of transactions executing concurrently [2, 6, 10] with respect to the fluctuating contention. Our results showed reduced resource usage without loss of performance in applications that exhibited fluctuating contention. We have also proposed and evaluated a novel scheduling techniques, Steal-on-Abort to avoid conflicts among transactions [8, 11, 14, 15].

Distributed STM

Most research on Software TM has focused on multiprocessor architectures (i.e. the architecture provides a cache coherent shared memory view). We have developed the first distributed software transactional memory research platform, called DiSTM, to investigate TM coherence on clusters [3, 7, 16]. In particular, we are investigating efficient protocols and structures for a TM implementation when the underlying hardware does not support shared memory.

Lee-TM Benchmark

We have created a TM benchmark based on a real-world application, [click here].

Publications

[20] Daniel Goodman, Behram Khan, Salman Khan, Behram Khan, Mikel Luján, and Ian Watson.
Software transactional memories for Scala.
In the Journal of Parallel and Distributed Computing, October 2012.

[19] Daniel Goodman, Behram Khan, Salman Khan, Chris Kirkham, Mikel Lujan and Ian Watson.
MUTS: Native Scala Constructs for Software Transactional Memory.
In Proceedings of Scala Days 2011, Stanford CA, June 2011.

[18] Behram Khan, Matthew Horsnell, Mikel Luján, Andrew Dinn and Ian Watson.
Exploiting object structure in hardware transactional memory.
In Proceedings of the European Conference on Parallel Processing (EUROPAR'10), Ischia-Naples, Italy, August 2010.

[17] Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn and Ian Watson.
Scalable Object-Aware Hardware Transactinal Memory.
International Journal of Computer Systems Science & Engineering. Vol. 24(5), pp. 303-315, 2009.
[PDF] [BibTeX]

[16] Christos Kotselidis, Mikel Luján, Mohammad Ansari, Konstantinos Malakasis, Behram Khan, Chris Kirkham and Ian Watson.
Clustering JVMs with Software Transactional Memory Support.
In Proceedings of the 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2010.
[PDF] [BibTex]

[15] Mohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris Kirkham and Ian Watson.
Improving Performance by Reducing Aborts in Hardware Transactional Memory.
In Proceedings of the 5th International Conference on High Performance and Embedded Architectures and Compilers (HIPEAC'10), LNCS 5952, pp 35-49, 2010.
[PDF] [BibTex]

[14] Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham and Ian Watson.
Transaction Reordering to Reduce Aborts in Software Transactional Memory.
In Transactions on High Performance and Embedded Architectures and Compilers (HIPEAC Journal), vol 4(4), 2009.
[PDF] [BibTex]

[13] Mohammad Ansari, Christos Kotselidis, Mikel Luján, Chris Kirkham and Ian Watson.
On the Performance of Contention Managers for Complex Transactional Memory Benchmarks.
In Proceedings of the 8th International Symposium on Parallel and Distributed Computing (ISPDC'09), July 2009.
[PDF] [BibTex]

[12] Mohammad Ansari, Kim Jarvis, Christos Kotselidis, Mikel Luján, Chris Kirkham and Ian Watson.
Profiling Transactional Memory Applications.
In Proceedings of the 17th International Conference on Parallel, Distributed, and Network-based Processing (PDP'09), February 2009.
[PDF] [BibTex]

[11] Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham and Ian Watson.
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering.
In Proceedings of the 4th International Conference on High Performance and Embedded Architectures and Compilers (HIPEAC'09), January 2009.
[PDF] [BibTex]

[10] Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham and Ian Watson.
Robust Adaptation to Available Parallelism in Transactional Memory Applications.
In Transactions on High Performance and Embedded Architectures and Compilers, vol. 3(4), 2008.
[PDF] [BibTex]

[9] Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, and Ian Watson.
An Object-Aware Hardware Transactional Memory System
In Proceedings of the International Conference on High Performance Computing and Communications (HPCC), September 2008.
[PDF] [BibTex]

[8] Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham and Ian Watson.
Steal-on-abort: Dynamic Transaction Reordering to Reduce Conflicts in Transactional Memory.
In the Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP'08), June 2008.
[PDF] [BibTex]

[7] Christos Kotselidis, Mohammad Ansari, Kim Jarvis, Mikel Luján, Chris Kirkham and Ian Watson.
DiSTM: A Software Transactional Memory Framework for Clusters.
In Proceedings of the International Conference on Parallel Processing (ICPP'08), Portland, OR, USA, September 2008.
[PDF] [BibTeX]

[6] Mohammad Ansari, Christos Kotselidis, Kim Jarvis, Mikel Luján, Chris Kirkham and Ian Watson.
Advanced Concurrency Control for Transactional Memory using Transaction Commit Rate.
In Proceedings of the European Conference on Parallel Processing (EUROPAR'08), Las Palmas, August 2008.
[PDF] [BibTeX]

[5] Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, and Ian Watson.
A First Insight into Object-Aware Hardware Transactional Memory.
In Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2008), Munich, Germany, June 2008.
[PDF] [BibTeX]

[4] Mohammad Ansari, Christos Kotselidis, Kim Jarvis, Mikel Luján, Chris Kirkham, and Ian Watson.
Lee-TM: A Non-trivial Benchmark for Transactional Memory.
In Proceedings of the 8th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP 2008), Aiya Napa, Cyprus, June 2008.
[PDF] [BibTeX]

[3] Christos Kotselidis, Mohammad Ansari, Kim Jarvis, Mikel Luján, Chris Kirkham, and Ian Watson. Investigating Software Transactional Memory on Clusters.
In Proceedings of the 10th International Workshop on Java and Components for Parallelism, Distribution and Concurrency (IWJPDC'08), Miami, FL, USA, April 2008.
[PDF] [BibTeX]

[2] Mohammad Ansari, Christos Kotselidis, Kim Jarvis, Mikel Luján, Chris Kirkham and Ian Watson.
Adaptive Concurrency Control for Transactional Memory.
In the 1st Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG'08), Goteborg, Sweden, January 2008.
[PDF] [BibTeX]

[1] Ian Watson, Chris Kirkham and Mikel Luján.
A Study of a Transactional Parallel Routing Algorithm.
In Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 2007, pp 388-398.
[PDF] [BibTex] [source code]

Acknowledgment

This project is funded by EPSRC.

Project Members