School of Computer Science Intranet
Low power logic design
We here in APT are developing wider interests in low-power systems than just the asynchronous logic work. Click here to see the PREST project. Below are some links which may illustrate some interesting areas in this (wide) field.
This page will undergo more development in the (hopefully near) future. In the mean time a selection of links is provided for general interest.
- ACMOS (University of Southern California)
- Low-Power Wireless System Design (Berkeley Infopad).
- CLPE Home Page (Center for Low Power Electronics)
- Physics of Computation at CalTech.
- The PowerPack Consortium.
- Low-Power CMOS Solutions
- Reversible Logic.
- MIT AI lab. Reversible logic
- More reversible logic publications
- Ultra-Low Power CMOS Design Using Reversible Logic
- Low-Power Digital ASIC Design
- Low-Power CAD
- Designing for Low Power
- Asynchronous Low Power Design Projects
- Design for Low Power (German)
- Low Power Software Page
Low power cell libraries
- Low Power Design tools (Berkeley).
- Stanford low power CAD group.
- ASC (Alternative System Concepts, Inc.): VHDL synthesis
- EPIC: PowerMill and AMPS
- Genashor: Xpower
- Synopsys: Power Family
- Veritools: Power_tool
- Watt Watcher
- The Ultra Low Power Wireless Sensor Project Home Page
- SPIFFEE, a low power FFT processor chip
- BDTI - Low Power Programmable DSPs
- Adiabatic Low Power Design Techniques
- Design Analysis and Synthesis for Low Power
- Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology