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Adaptive Pipeline Depth Control for Processor Power-Management

A. Efthymiou, J.D. Garside


A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded. Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them `permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.

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