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Luis Tarazona Duarte


This thesis evaluates the capabilities and limitations of the syntax-directed ap- proach to synthesise high-performance asynchronous systems and proposes a num- ber of optimisations to improve the performance of the synthesised circuits. The first part of this work explores new methods for improving the perfor- mance of asynchronous circuits synthesised from syntax-directed descriptions, targeting handshake circuits and using the Balsa synthesis system as the research framework. This includes investigating description styles and the use of language constructs that result in faster circuits. A number of new peephole optimisations based on the previous observations are also presented. The second part investigates the performance of a new, token-flow based syn- thesiser for the Balsa language called Teak. A set of optimisations based in circuit transformations and buffering strategies are proposed in order to improve the performance of Teak circuits. These optimisations have been automated and incorporated into the Teak synthesiser. All optimisations target dual-rail, quasi-delay-insensitive implementations as this is a robust approach that helps to reduce the impact of the timing closure problem within modern fabrication processes variability. The techniques and optimisations presented here has been tested in a set of non-trivial examples in- cluding a 32-bit RISC processor. The use of the proposed techniques result in optimised compositions of hand- shake circuits and Teak components that generally synthesise into faster cir- cuits.

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