On-Chip and Inter-Chip networks for Modelling Large-Scale Neural Systems

S.Furber, S.Temple, A.Brown

Abstract

The real-time modelling of large systems of spiking neurons is computationally very demanding in terms of processing power, synaptic weight memory requirements and communication throughput. We propose to build a high-performance computer for this purpose with a multicast communication infrastructure inspired by neurobiology. The core component will be a chip multiprocessor incorporating some tens of small embedded processors, interconnected by an NoC that carries spike events between processors of the same or different chips. The design emphasises modelling flexibility, power efficiency, and fault tolerance, and is intended to yield a general-purpose platform for the real-time simulation of large-scale spiking neural systems.

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