Fault-Tolerant Delay-Insensitive Communication

Yebin Shi

Abstract

The SpiNNaker machine is a massively-parallel computer aimed at modelling large-scale systems of spiking neurons. It employs a large number of multicore processor integrated circuits in a two-dimensional mesh using asynchronous inter-chip interconnect. Its scale demands that it be robust to the failure of individual components, and in the course of its development fault-tolerance techniques have been employed at many levels in its design. Fault tolerance has also become a major concern for modern VLSI design because deep-submicron technology is more vulnerable to faults than earlier technologies with larger feature sizes due to the increased parameter variability that results from near-atomic scales. Asynchronous interconnect is an alternative to synchronous interconnect that offers advantages such as low power and low electro-magnetic interference, and is therefore a promising interconnect solution for SpiNNaker and for deep-submicron technologies in general. However, asynchronous interconnect suffers from the problem that any malfunction is likely to result in circuit-level deadlock, recovery from which can be difficult as both ends of the deadlocked link must coordinate recovery action. The work described in this thesis investigates the influence of transient off-chip glitches on the robustness of the delay-insensitive asynchronous interconnect which is used in the SpiNNaker project. In addition to packet corruption, deadlock may occur in the presence of glitches. Techniques are proposed in the off-chip interface circuits to filter glitches, correct illegal symbols, minimise the occurrence of deadlock and allow independent reset of the link from either end. Simulation results demonstrate the effectiveness of these techniques primarily to minimise the occurrence of deadlock caused by single transient glitches.

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