Copy-Back Cache Organisation For An Asynchronous Microprocessor

Daranee Hormdee

Abstract

Over the last decade asynchronous design has re-emerged as a viable alternative to clocked design with mounting evidence of competitive performance, power efficiency and electromagnetic compatibility compared to the more mainstream synchronous style. However, although significant effort has been expended in the design of asynchronous processors, the design of asynchronous caches has been relatively neglected.

This thesis presents an asynchronous cache architecture the logical choice for use with an asynchronous microprocessor. The design presented here provides the processor with a unified, dual-ported view of its memory subsystem using multiple interleaved blocks. Each block has separate instruction and data line-buffers effectively acting as level-zero (L0) cache, making the cache access time highly variable. The cache employs a copy-back write strategy to support a high-performance embedded processor core.

The other key memory system component required for performance improvement, especially when combined with a copy-back cache, is a victim cache; an asynchronous implementation of a victim cache is presented in the second part of this thesis. Together, the resultant structure forms an asynchronous cache system for AMULET3, the third generation fully asynchronous implementation of the ARM processor. Although the whole design is optimised for the AMULET3 microprocessor core, the techniques employed are generally applicable to any asynchronous processor.

The proposed cache architecture is extensively evaluated using simulations, and the effectiveness of various alternative configurations is measured to arrive at a suitable trade-off between cost, complexity and performance. The simulations highlight some unusual aspects of the behaviour of asynchronous memory hierarchies.

The thesis is available by ftp in postscript (709KB compressed) or pdf (1.1MB) form.