The Design of a Self-timed Low Power FIFO using a Word-slice Structure

Kyoung Kuen Yi

Abstract

A new structure for a FIFO (First In First Out memory), the Word-Slice FIFO, has been developed in order to attain high performance and low power. Conventional asynchronous micropipeline structures have two major problems when used as a FIFO. The first problem is high power consumption and the second is low performance. The serial structure of the data path and the control mechanism of the micropipeline cause the problems.

This dissertation presents solutions to these problems using a new FIFO structure. Each word of the memory element has its own local controller, which allows the FIFO structure to be as simple as a micropipeline FIFO. All memory elements are arranged in parallel for high performance. Only one local controller and one memory element are activated for a data transfer for low power consumption.

Post-layout simulation, in a 0.35 micron technology, shows that a Word-Slice FIFO which has 16 words of 32-bit memory consumes 183.5 pJ to transfer data when half the data bits are toggled. In a corresponding micropipeline FIFO, the energy used for the same data transfer is measured as 388.1 pJ. Data delays from input to output are 3.8 ns and 12.4 ns for the Word-Slice and micropipeline structure respectively.

The thesis is available by ftp in postscript (980kB - gzipped) or pdf form (3.8MB)